ST10F280
3 - FUNCTIONAL DESCRIPTION
The architecture of the ST10F280 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The
Figure 3 : Block Diagram
block diagram gives an overview of the different
on-chip components and the high bandwidth inter-
nal bus structure of the ST10F280.
32
512K Byte
Flash Memory
CPU-Core and MAC Unit
16
16
2K Byte
Internal
RAM
16K Byte
XRAM
P4.5 CAN1_RxD
P4.6 CAN1_TxD
P4.4 CAN2_RxD
P4.7 CAN2_TxD
CAN1
CAN2
16
16
PEC
Interrupt Controller
Watchdog
Oscillator
and PLL
XTAL1 XTAL2
16
3.3V Voltage
Regulator
16
16
8
Port 6
8
Port 5
16
BRG
Port 3
15
BRG
XPORT10 XPORT9 XPWM XTIMER
16
16
4
XADCINJ
16
Port 7
Port 8
8
8
P7.7 Trigger for ADC
channel injection
External connexion
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