ST10R272 View Datasheet(PDF) - STMicroelectronics
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Description
Manufacturer
ST10R272 Datasheet PDF : 77 Pages
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ST10R272L - ELECTRICAL CHARACTERISTICS
16.3.7 External Hardware Reset
VDD = 3.3 V ± 0.3 V
VSS = 0 V
TA = -40 to +85 °C
CL = 50 pF
Parameter
Symbol
Max. CPU Clock
= 50 MHz
min.
max.
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
Sync. RSTIN low time1) t70 SR 50
–
4 TCL + 10 –
ns
RSTIN low to internal
reset sequence start
t71 CC 4
16
4
16
TCL
internal reset sequence, t72 CC 1024
1024
1024
1024
TCL
(RSTIN internally pulled
low)
RSTIN rising edge to inter- t73 CC 4
6
4
6
TCL
nal reset condition end
PORT0 system start-up t74 SR 100
–
100
–
ns
configuration setup to
RSTIN rising edge 2))
PORT0 system start-up t75 SR 1
6
1
6
TCL
configuration hold after
RSTIN rising edge
Bus signals drive from
internal reset end
t76 CC 0
20
0
20
ns
RSTIN low to signals
release
t77 CC –
50
–
50
ns
ALE rising edge from inter- t78 CC 8
8
8
8
TCL
nal reset condition end
Async. RSTIN low time1 t79 SR 1500
–
1500
–
ns
Table 21 External hardware reset
1) On power-up reset, the RSTIN pin must be asserted until a stable clock signal is available
(about 10...50 ms to allow the on-chip oscillator to stabilize) and until System Start-up Con-
figuration is correct on PORT0 (about 50 µs for internal pullup devices to load 50 pF from
VILmin to VIHmin).
2) The value of bits 0 (EMU), 1 (ADAPT), 13 to 15 (Clock Configuration) are loaded during
hardware reset as long as internal reset signal is active, and have an immediate effect on
the system.
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