ST10R272L - ELECTRICAL CHARACTERISTICS
1)
RSTIN
Internal
Reset
Signal
ALE
t792)
RD, WR
3)
PORT0
t73 t76
t78
t74
t75
4)
PORT1
(Demux Bus)
RSTOUT 5)
6)
Other IOs
t77
Figure 27 External asynchronous hardware reset (power-up reset): Vpp low
1 The ST10R272L is reset in its default state asynchronously with RSTIN. The internal
RAM content may be altered if an internal write access is in progress.
2 On power-up, RSTIN must be asserted t79 after a stabilized CPU clock signal is available.
3 Internal pullup devices are active on the PORT0 lines, so - input level is high if the respec-
tive pin is left open - or is low if the respective pin is connected to an external pulldown
device.
4 The ST10R272L starts execution here at address 00’0000h.
5 RSTOUT stays active until execution of the EINIT (end of initialization) instruction.
6 Activation of the IO pins is controlled by software
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