ST10R272L - ELECTRICAL CHARACTERISTICS
.
RSTIN
Internal
Reset
Signal
ALE
t70
t711)
t722)
t73 t76
3)
t78
RD, WR
4)
PORT0
t74
t75
5)
PORT1
(Demux Bus)
RSTOUT 6)
7)
Other IOs
t77
Figure 28 External synchronous hardware reset (warm reset): Vpp high
1 The pending internal hold states are cancelled and the current internal access cycle (if
any) is completed.
2 RSTIN pulled low by internal device during internal reset sequence.
3 The reset condition may ends here if RSTIN pin is sampled high after t72.
4 Internal pullup devices are active on the PORT0 lines. Their input level is high if the
respective pin is left open, or is low if the respective pin is connected to an external pull-
down device by resistive high (pullup) after t64.
5 The ST10R272L starts execution here at address 00’0000h.
6 RSTOUT stays active until execution of the EINIT (End of Initialization) instruction.
7 Activation of the IO pins is controlled by software.
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