ST7282B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7282B5

ROM FROM EPROM

STMicroelectronics 

ST7282A5 - ST7282B5 - ROM FROM EPROM

Figure 2. External Interrupt Options

INTP

INTN

0

0

0

1

1

0

1

1

I1 External Interrupt Options

Negative edge and Low level sensitive

Negative edge only

Positive edge only

Positive and negative edge sensitive

2.2 LCD controller/driver

The LCD module contains an LCD controller/driver with 20 segment and 16 backplane outputs able to

drive up to 20 x 16 = 320 segments. The LCD control logic reads automatically data from the LCD-RAM

independently from the ST72 core.

Two signals (LCF32K,LCSYNCHINOUT) can be activated on pins PC0, PC1 to connect a slave display

chip for expanding the number of segments. To activate these pins as LCF32K, LCSYNCHINOUT, bit0 of

register LCD Ctrl.2 (0027H) has to be set. During reset this bit is cleared.

VLCD must never be below VDD.

2.2.1 Address mapping of the picture elements

The LCD-RAM is located in the address region of the ST72 data space from address 40H - 7FH.

The LCD forms a matrix of 20 segment lines ( columns ) and 16 backplane lines ( rows ). Each bit of the

LCD-RAM is mapped to one dot of the LCD matrix according to fig. 1. If a bit is set, the corresponding LCD

segment is switched on, if it is reset, the segment is switched off.

After reset, the LCD-RAM is not initialized and contains arbitrary information. As the LCD control register

is cleared, the LCD is completely switched off.

In halt mode no clock for the LCD module is available from the main oscillator. The LCD module is

switched off in halt mode.

The input frequency of the LCD controller is fOSC/2 (4.275MHz).

A 32kHz stand by oscillator is not available. Therefore the mode FEXT (C5, C4, C3 = 001) of LCD control

register cannot be used.

In any case a missing LCD clock ( no oscillator active, broken crystal etc. ) is detected by a clock super-

visor circuit which switches all segment and common lines to ground to avoid destructive DC levels at the

LCD.

If the LCD clock is not missing but far too slow (e.g. due to incorrect setting of C5, C4, C3 in LCD control

register) the LCD is switched off periodically. This situation has to be avoided.

A division factor of +256 is recommended for the prescaler (C5, C4, C3 = 110; fOUT = 16.699KHz). With

this setting of the predevider, frame frequencies of 132.2Hz, 66.1Hz, 44.1Hz and 33.1Hz can be generat-

ed.

The frequency out of the prescaler must not be below 15KHz in order not to switch off the display through

the LCD oscillator supervisor.

To activate segments and backplanes, data and option register bits of the corresponding combiport pins

have to be set to 1. During reset data and option register bits of combiports are set to 1.

Family

ST7

Issuer Ref.

PG-RO

Chrono

97115

7282A5B5

March 26, 1997

Previous Ref

Edition

Target C

Page 12/23

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