ST7282B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7282B5

ROM FROM EPROM

STMicroelectronics 

ST7282A5 - ST7282B5 - ROM FROM EPROM

Figure 9. Peripheral Interface Configuration of Serial I/O

DOUT / PA7

PP / OD

OPR

MUX

0

1

DR

OUT

SDA / PA6

IN

DR

SERIAL

I/O

CLOCK

SCL / PA5

DR

INTERFA C.DS4

2.8 RAM

The RAM is located in the address range A0H-

3FFH.

300H-3FFH may be used as Stack area.

2.9 EEPROM

The 512 bytes EEPROM is located at addresses

0E00 - 0FFF. 2 cells of 256 bytes each or one cell

of 512 bytes may be used. EEPROM control regis-

ter EECR (adr. 014H) is used to control the differ-

ent operation modes of the range 0E00H - 0EFFH,

EEPROM control register EECR2 (adr. 015H) that

of range 0F00H - 0FFFH. Some of its bits are read

only, some are write only. So no single bit instruc-

tions are allowed.

To avoid destruction of data during power up or

down, the reset pin directly desactivates the

chargepump of EEPROM cells.

The EEPROM can be used for data storage only,

no program execution and no read modify write in-

structions (single bit, increment, decrement) are

possible.

After bit E2LAT of EECR goes to low, there should

not be a read operation during the next 20 µsec.

A parallel programming mode for 8 bytes is availa-

ble. No clear is needed before a write.

Two cells of 256 bytes are used, parallel program-

ming of bytes in each cell is possible. This should

be avoided however, to keep software compatitility

between all future versions and ROM versions,

that have only one physical register, that will be

addressed through two different addresses 14H

and 15H.

Family

ST7

Issuer Ref.

PG-RO

Chrono

97115

7282A5B5

March 26, 1997

Previous Ref

Edition

Target C

Page 19/23

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