ST7282B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7282B5

ROM FROM EPROM

STMicroelectronics 

ST7282A5 - ST7282B5 - ROM FROM EPROM

Figure 8. Address Mapping of the LCD-RAM MUX4

BP1 bit0

ADRESS

BP2 bit1

ES

BP3 bit2

64 ... 7F

BP4 bit3 60 61 62 63 40 41 -- 47 48 49 --

--

--

5E

5

F

not used

S S SSSS

E E EEEE

G G GGGG

-11 -10 -9 -8 -7 -6

S SS

E EE

G GG

0 12

S (SEG21

E ... SEG24

G are not

24 available)

2.3 TIMER 4

16 bit autoreload timer with 2 capture inputs con-

nected to PA0, PA1 (see spec. ST7TIM4). The in-

put clock of the timer is fosc divided by 2.

2.4 WATCHDOG

The WD2 is used to reset the ST7282 B5 after a

certain period of time in the range of 2.8 msec up

to 184 msec when fOSC = 8.55 MHz is used.

WD2 will be activated, if bit0 in Watchdog Reg.

(Adr. 12h) is set ("1"). Once WD2 is running, any

software access to bit0 in Watchdog Reg. will NOT

influence WD2. However, a RESET signal (either

externally or caused by WD2) will reset bit0 of

Watchdog Reg.

After a RESET, WD2 is deactivated and set to it's

longest period ( 184 msec for fOSC = 8.55 MHz ).

WD2 is able to produce a SW-Reset ( bit0 set to

"1", bit1 to "0" ).

Dedication address of WD2 is 12h .

If WD2 is enabled, any stop instruction will gener-

ate a reset. However, the use of a stop instruction

(HALT) is not recommended in this case.

2.5 I/O PORTS

Pins PD0 ... PD7, PE0 ... PE3, PF0 ... PF7, PG0 ...

PG7 and PH0 ... PH7 are of type LCIO.

Pins PA0 ... PA7, PB0 ... PB7 and PC0 ... PC7 are

of type IO3 and can also be used as analog inputs.

The interrupt outputs of PORT A, PORT B, PORT

C, PORT D, PORT E, PORT F, PORT G and

PORT H are anded and connected to the interrupt

input I1 of core ( start address FFFAH ). So every

port pin which is programmed as an input with in-

terrupt enabled can generate an interrupt. If more

than one port pin is programmed as an interrupt in-

put, overlapping interrupts cannot be detected due

to the AND function.

PA0, PA1 are also used as CP1, CP2 inputs of

TIMER 4.

The pins PA5 ... PA7 are also used by the serial

I/O ( see fig. 2 ). PA5 is connected with SCL (

clock input ), PA6 is connected with SDA ( data in-

put ) and PA7 is connected with DOUT ( data out-

put ) of the SIO.

For serial input operation PA5 and PA6 have to be

programmed as inputs. For serial output PA7 has

to be programmed as open drain output ( DDR = 1,

OPR = 0 ). In this operation mode the output of the

SIO shift register instead of the port data register is

connected to the port buffer. When PA7 is pro-

grammed as push pull output ( DDR = 1, OPR

= 1 ), the port data register is connected to the port

buffer.

When the SIO pins are not used PA5 ... PA7 can

be used as any other I/O pin (PA7 not in open

drain output mode).

After reset ports PA0 ... PA7, PB0 ... PB7 and PC0

... PC6 are in input mode with pull up resistors

switched on and interrupt disabled.

Family

ST7

Issuer Ref.

PG-RO

Chrono

97115

7282A5B5

March 26, 1997

Previous Ref

Edition

Target C

Page 17/23

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