STA320
For example, SAI=1110 and SAIFB=1 would specify Right-Justified 16-bit data, LSB-First.
Table 4 below lists the serial audio input formats supported by STA320 as related to BICKI = 32/48/64fs, where
sampling rate fs = 32/44.1/48/88.2/96kHz.
Table 12. Supported Serial Audio Input Formats
BICKI
32fs
48fs
64fs
SAI (3...0)
1100
1110
0100
0100
1000
0100
1100
0001
0101
1001
1101
0010
0110
1010
1110
0000
0100
1000
0000
1100
0001
0101
1001
1101
0010
0110
1010
1110
SAIFB
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
Interface Format
I2S 15bit Data
Left/Right-Justified 16bit Data
I2S 23bit Data
I2S 20bit Data
I2S 18bit Data
MSB First I2S 16bit Data
LSB First I2S 16bit Data
Left-Justified 24bit Data
Left-Justified 20bit Data
Left-Justified 18bit Data
Left-Justified 16bit Data
Right-Justified 24bit Data
Right-Justified 20bit Data
Right-Justified 18bit Data
Right-Justified 16bit Data
I2S 24bit Data
I2S 20bit Data
I2S 18bit Data
MSB First I2S 16bit Data
LSB First I2S 16bit Data
Left-Justified 24bit Data
Left-Justified 20bit Data
Left-Justified 18bit Data
Left-Justified 16bit Data
Right-Justified 24bit Data
Right-Justified 20bit Data
Right-Justified 18bit Data
Right-Justified 16bit Data
5.2.3 Delay Serial Clock Enable
BIT
R/W
RST
NAME
DESCRIPTION
5
R/W
0
DSCKE
Delay Serial Clock Enable:
0 – No serial clock delay
1 – Serial clock delay by 1 core clock cycle to tolerate anomalies
in some I2S master devices
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