STA320 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA320 Datasheet PDF : 37 Pages
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STA320
Table 8. Register Summary (continued)
Addr
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
Name
B2cf3
A1cf1
A1cf2
A1cf3
A2cf1
A2cf2
A2cf3
B0cf1
B0cf2
B0cf3
Cfud
MPCC1
MPCC2
DCC1
DCC2
FDRC1
FDRC2
Status
BC0
BS0
BS1
B1
B2
T
D7
C2B7
C3B23
C3B15
C3B7
C4B23
C4B15
C4B7
C5B23
C5B15
C5B7
MPCC15
MPCC7
DCC15
DCC7
FDRC15
FDRC7
PLLUL
RES
RES
RES
RES
RES
RES
D6
C2B6
C3B22
C3B14
C3B6
C4B22
C4B14
C4B6
C5B22
C5B14
C5B6
MPCC14
MPCC6
DCC14
DCC6
FDRC14
FDRC6
RES
RES
RES
RES
RES
RES
D5
C2B5
C3B21
C3B13
C3B5
C4B21
C4B13
C4B5
C5B21
C5B13
C5B5
MPCC13
MPCC5
DCC13
DCC5
FDRC13
FDRC5
RES
RES
RES
RES
RES
RES
D4
C2B4
C3B20
C3B12
C3B4
C4B20
C4B12
C4B4
C5B20
C5B12
C5B4
MPCC12
MPCC4
DCC12
DCC4
FDRC12
FDRC4
RES
RES
RES
RES
RES
RES
D3
D2
C2B3
C2B2
C3B19 C3B18
C3B11 C3B10
C3B3
C3B2
C4B19 C4B18
C4B11 C4B10
C4B3
C4B2
C5B19 C5B18
C5B11 C5B10
C5B3
C5B2
RA
R1
MPCC11 MPCC10
MPCC3 MPCC2
DCC11 DCC10
DCC3
DCC2
FDRC11 FDRC10
FDRC3 FDRC2
OCWARN TFAULT
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
D1
C2B1
C3B17
C3B9
C3B1
C4B17
C4B9
C4B1
C5B17
C5B9
C5B1
WA
MPCC9
MPCC1
DCC9
DCC1
FDRC9
FDRC1
FAULT
RES
BS9
RES
RES
RES
RES
D0
C2B0
C3B16
C3B8
C3B0
C4B16
C4B8
C4B0
C5B16
C5B8
C5B0
W1
MPCC8
MPCC0
DCC8
DCC0
FDRC8
FDRC0
TWARN
RES
BS8
RES
RES
RES
RES
5.1 Configuration Register A (address 00h)
D7
D6
D5
D4
FDRB
TWAB
TFRB
IR1
0
1
1
0
D3
D2
D1
D0
IR0
MCS2
MCS1
MCS0
0
0
1
1
5.1.1 Master Clock Select
BIT
R/W
RST
0
R/W
1
1
R/W
1
2
R/W
0
NAME
MCS0
MCS1
MCS2
DESCRIPTION
Master Clock Select : Selects the ratio between the input
I2S sample frequency and the input clock.
The STA320 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, 96kHz, Therefore the internal clock
will be:
– 32.768Mhz for 32kHz
– 45.1584Mhz for 44.1khz, 88.2kHz and 176.4kHz
– 49.152Mhz for 48kHz, 96kHz, and 192kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency(fs). The
relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (Input
Rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit deter-
mine the oversampling ratio used internally.
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