STA32813TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STA32813TR

2.1-channel high-efficiency digital audio system

STMicroelectronics 

STA328

Register description

Table 19. Serial input data timing characteristics (fs = 32 to 192 kHz)

Parameter in Figure 16

Value

BICKI frequency (slave mode)

BICKI pulse width low (T0) (slave mode)

BICKI pulse width high (T1) (slave mode)

BICKI active to LRCKI edge delay (T2)

BICKI active to LRCKI edge delay (T3)

SDI valid to BICKI active setup (T4)

BICKI active to SDI hold time (T5)

12.5 MHz max.

40 ns min.

40 ns min.

20 ns min.

20 ns min.

20 ns min.

20 ns min.

Figure 16. Serial input data timing

T2

LRCKI

BICKI

SDI

T3

T4

T5

T1

T0

Table 20. Delay serial clock enable

Bit R/W RST

Name

Description

5

RW 0

DSCKE

Delay serial clock enable:

0: no serial clock delay

1: serial clock delay by 1 core clock cycle to tolerate

anomalies in some I2S master devices

Table 21. Channel input mapping

Bit R/W RST

Name

Description

6

RW 0

C1IM

7

RW 1

C2IM

0: processing channel 1 receives left I2S input

1: processing channel 1 receives right I2S input

0: processing channel 2 receives left I2S input

1: processing channel 2 receives right I2S input

Each channel received via I2S can be mapped to any internal processing channel via the

channel input mapping registers. This allows for flexibility in processing. The default settings

of these registers map each I2S input channel to its corresponding processing channel.

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