AT80251G2D-3CSUM(2006) View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT80251G2D-3CSUM
(Rev.:2006)

8/16-bit Microcontroller with Serial Communication Interfaces

Atmel Corporation 

Size and Execution Time

for Instruction Families

Table 20. Summary of Add and Subtract Instructions

AddADD <dest>, <src>dest opnd ← dest opnd + src opnd

SubtractSUB <dest>, <src>dest opnd ← dest opnd - src opnd

Add with CarryADDC <dest>, <src>(A) ← (A) + src opnd + (CY)

Subtract with BorrowSUBB <dest>, <src>(A) ← (A) - src opnd - (CY)

<dest>,

Mnemonic <src>(1)

Comments

Binary Mode

Source Mode

Bytes States Bytes States

A, Rn

Register to ACC

1

1

2

2

ADD

A, dir8

A, at Ri

Direct address to ACC

Indirect address to ACC

2

1(2)

2

1(2)

1

2

2

3

A, #data

Immediate data to ACC

2

1

2

1

Rmd, Rms

Byte register to/from byte register

3

2

2

1

WRjd, WRjs Word register to/from word register

3

3

2

2

DRkd, DRks Dword register to/from dword register

3

5

2

4

Rm, #data

Immediate 8-bit data to/from byte

register

4

3

3

2

WRj, #data16

Immediate 16-bit data to/from word

register

5

4

4

3

DRk,

#0data16

16-bit unsigned immediate data

to/from dword register

5

6

4

5

ADD/SUB Rm, dir8

Direct address (on-chip RAM or SFR)

to/from byte register

4

3(2)

3

2(2)

WRj, dir8

Direct address (on-chip RAM or SFR)

to/from word register

4

4

3

3

Rm, dir16

Direct address (64K) to/from byte

register

5

3(3)

4

2(3)

WRj, dir16

Direct address (64K) to/from word

register

5

4(4)

4

3(4)

Rm, at WRj

Indirect address (64K) to/from byte

register

4

3(3)

3

2(3)

Rm, at DRk

Indirect address (16M) to/from byte

register

4

4(3)

3

3(3)

A, Rn

Register to/from ACC with carry

1

1

2

2

ADDC/SU

BB

A, dir8

A, at Ri

Direct address (on-chip RAM or SFR)

to/from ACC with carry

2

Indirect address to/from ACC with

carry

1

1(2)

2

1(2)

2

2

3

A, #data

Immediate data to/from ACC with

carry

2

1

2

1

Notes:

1. A shaded cell denotes an instruction in the C51 Architecture.

2. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.

Add 2 if it addresses a Peripheral SFR.

3. If this instruction addresses external memory location, add N+2 to the number of

states (N: number of wait states).

24 AT/TSC8x251G2D

4135F–8051–11/06

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