Notes:
1. Logical instructions that affect a bit are in Table 27.
2. A shaded cell denotes an instruction in the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Table 23. Summary of Logical Instructions (2/2)
Shift Left LogicalSLL <dest><dest>0 ← 0
<dest>n+1 ← <dest>n, n = 0..msb-1
(CY) ← <dest>msb
Shift Right ArithmeticSRA <dest><dest>msb ← <dest>msb
<dest>n-1 ← <dest>n, n = msb..1
(CY) ← <dest>0
Shift Right LogicalSRL <dest><dest>msb ← 0
<dest>n-1 ← <dest>n, n = msb..1
(CY) ← <dest>0
SwapSWAP AA3:0 A7:4
Mnemonic
<dest>,
<src>(1)
Comments
Binary Mode Source Mode
Bytes States Bytes States
Rm
Shift byte register left through the
MSB
3
2
2
1
SLL
WRj
Shift word register left through the
MSB
3
2
2
1
SRA
Rm
Shift byte register right
WRj
Shift word register right
3
2
2
1
3
2
2
1
Rm
Shift byte register left
SRL
WRj
Shift word register left
3
2
2
1
3
2
2
1
SWAP
A
Swap nibbles within ACC
1
2
1
2
Note: 1. A shaded cell denotes an instruction in the C51 Architecture.
28 AT/TSC8x251G2D
4135F–8051–11/06