Table 22. Summary of Compare Instructions
CompareCMP <dest>, <src>dest opnd - src opnd
<dest>,
Mnemonic <src>(2)
Comments
Rmd, Rms Register with register
WRjd,
WRjs
Word register with word register
DRkd,
DRks
Dword register with dword register
Rm, #data Register with immediate data
WRj,
#data16
Word register with immediate 16-bit data
CMP
DRk,
#0data16
DRk,
#1data16
Dword register with zero-extended 16-bit
immediate data
Dword register with one-extended 16-bit
immediate data
Rm, dir8
Direct address (on-chip RAM or SFR) with
byte register
WRj, dir8
Direct address (on-chip RAM or SFR) with
word register
Rm, dir16 Direct address (64K) with byte register
WRj, dir16 Direct address (64K) with word register
Rm, at WRj Indirect address (64K) with byte register
Rm, at DRk Indirect address (16M) with byte register
Binary Mode Source Mode
Bytes States Bytes States
3
2
2
1
3
3
2
2
3
5
2
4
4
3
3
2
5
4
4
3
5
6
4
5
5
6
4
5
4
3(1)
3
2(1)
4
4
3
3
5
3(2)
4
2(2)
5
4(3)
4
3(3)
4
3(2)
3
2(2)
4
4(2)
3
3(2)
Notes:
1. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
2. If this instruction addresses external memory location, add N+2 to the number of
states (N: number of wait states).
3. If this instruction addresses external memory location, add 2(N+2) to the number of
states (N: number of wait states).
26 AT/TSC8x251G2D
4135F–8051–11/06