TS68230 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

TS68230

HMOS PARALLEL INTERFACE/TIMER

STMicroelectronics 

TS68230

2. This specification applies only when a pulsed handshake option is chosen and the pulse is not shortened due to an

early asserted edge of H1(H3).

3. The maximum value is caused by a peripheral access (H1(H3) asserted) and bus access (CS asserted) occurring

at the same time.

4. Synchronized means that the input signal has been seen by the PI/T on the appropriate edge of the clock (rising

edge for H1(H3) and falling edge for CS). (Refer to the 1.4. Bus Interface Operation for the exception concerning

CS).

7.1. PIN ASSIGNMENTS

48-Pin Dual-in-Line

52-Pin Quad Pack (PLCC)

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