PSD834F3A-12UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD834F3A-12UI Datasheet PDF : 128 Pages
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AC/DC parameters
PSD8XXFX
Table 63. Port A Peripheral Data mode READ timing (3V devices)
Symbol
Parameter
Conditions
-12
-15
-20
Turbo
Unit
Min Max Min Max Min Max off
tAVQV–PA
tSLQV–PA
tRLQV–PA
Address valid to data valid
CSI valid to data valid
RD to data valid
RD to data valid 8031 mode
(1)
(2)(3)
50
50
50 + 20 ns
37
45
50 + 20 ns
37
40
45
ns
45
45
50
ns
tDVQV–PA
Data In to data Out valid
38
40
45
ns
tQXRH–PA
tRLRH–PA
tRHQZ–PA
RD data hold time
RD pulse width
RD to data high-Z
0
0
0
ns
(2)
36
36
46
ns
(2)
36
40
45
ns
1. Any input used to select port A Data Peripheral mode.
2. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
3. Data is already stable on port A.
Figure 47. Peripheral I/O WRITE timing
ALE /AS
A/D BUS
ADDRESS
DATA OUT
tWLQV (PA)
tWHQZ (PA)
WR
tDVQV (PA)
PORT A
DATA OUT
AI02898
Table 64. Port A Peripheral Data mode WRITE timing (5 V devices)
Symbol
Parameter
Conditions
-70
-90
-15
Unit
Min Max Min Max Min Max
tWLQV–PA WR to data propagation delay
(1)
tDVQV–PA
Data to port A data propagation delay
(2)
tWHQZ–PA WR invalid to port A tri-state
(1)
1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
2. Data stable on ADIO pins to data on port A.
25
35
40 ns
22
30
38 ns
20
25
33 ns
112/128
Doc ID 7833 Rev 7
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