PSD834F3A-12UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD834F3A-12UI Datasheet PDF : 128 Pages
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PSD8XXFX
AC/DC parameters
Table 69. ISC timing (3 V devices)
Symbol
Parameter
Conditions
tISCCF
Clock (TCK, PC1) frequency (except for
PLD)
(1)
tISCCH
Clock (TCK, PC1) high time (except for
PLD)
(1)
tISCCL
Clock (TCK, PC1) low time (except for
PLD)
(1)
tISCCFP Clock (TCK, PC1) frequency (PLD only)
(2)
tISCCHP Clock (TCK, PC1) high time (PLD only)
(2)
tISCCLP Clock (TCK, PC1) low time (PLD only)
(2)
tISCPSU ISC port setup time
tISCPH ISC port hold up time
tISCPCO ISC port clock to output
tISCPZV ISC port high-Impedance to valid Output
tISCPVZ ISC port valid Output to high-Impedance
1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For program or erase PLD only.
-12
-15
-20
Unit
Min Max Min Max Min Max
12
10
9 MHz
40
45
51
ns
40
45
51
ns
2
2
2 MHz
240
240
240
ns
240
240
240
ns
12
13
15
ns
5
5
5
ns
30
36
40 ns
30
36
40 ns
30
36
40 ns
Table 70. Power-down timing (5 V devices)
Symbol
Parameter
Conditions
tLVDV
tCLWH
ALE access time from Power-down
Maximum delay from APD Enable to
Internal PDN valid signal
1. tCLCL is the period of CLKIN (PD1).
Using CLKIN
(PD1)
-70
-90
-15
Unit
Min Max Min Max Min Max
80
90
150 ns
15 * tCLCL(1)
µs
Table 71. Power-down timing (3 V devices)
Symbol
Parameter
Conditions
tLVDV
tCLWH
ALE access time from Power-down
Maximum Delay from APD Enable to
Internal PDN valid Signal
1. tCLCL is the period of CLKIN (PD1).
Using CLKIN
(PD1)
-12
-15
-20
Unit
Min Max Min Max Min Max
145
150
200 ns
15 * tCLCL(1)
µs
Doc ID 7833 Rev 7
115/128
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