PSD834F3A-12UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD834F3A-12UI Datasheet PDF : 128 Pages
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PSD8XXFX
AC/DC parameters
Table 65. Port A Peripheral Data mode WRITE timing (3 V devices)
Symbol
Parameter
Conditions
-12
-15
-20
Unit
Min Max Min Max Min Max
tWLQV–PA WR to data propagation delay
(1)
tDVQV–PA
Data to port A data propagation delay
(2)
tWHQZ–PA WR invalid to port A tri-state
(1)
1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
2. Data stable on ADIO pins to data on port A.
42
45
55 ns
38
40
45 ns
33
33
35 ns
Figure 48. Reset (RESET) timing
VCC
RESET
VCC(min)
tNLNH-PO
Power-On Reset
tOPR
tNLNH
tNLNH-A
Warm Reset
Table 66. Reset (RESET) timing (5 V devices)
Symbol
Parameter
Conditions
Min
tNLNH
RESET active low time(1)
150
tNLNH–PO Power-on Reset active low time
1
tNLNH–A
Warm Reset (on the PSD834Fx)(2)
25
tOPR
RESET high to operational device
1. Reset (RESET) does not reset Flash memory program or erase cycles.
2. Warm reset aborts Flash memory program or erase cycles, and puts the device in READ mode.
Table 67. Reset (RESET) timing (3 V devices)
Symbol
Parameter
Conditions
Min
tNLNH
RESET active low time(1)
300
tNLNH–PO Power-on Reset active low time
1
tNLNH–A
Warm Reset (on the PSD834Fx)(2)
25
tOPR
RESET high to operational device
1. Reset (RESET) does not reset Flash memory program or erase cycles.
2. Warm reset aborts Flash memory program or erase cycles, and puts the device in READ mode.
tOPR
AI02866b
Max
Unit
ns
ms
µs
120
ns
Max
Unit
ns
ms
µs
300
ns
Doc ID 7833 Rev 7
113/128
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