Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
2.0
2.1
2.2
Architectural Overview
Principles of Operation
The FM2112 is an IEEE-compliant Ethernet bridge. For an in-depth
discussion of the principles of operation, see Clause 7 of the IEEE
802.1D-2004 specification.
Architectural Partitioning
The Intel®Ethernet Switch Family is architecturally partitioned into five
major blocks, as shown in Figure 4. They are:
• Ethernet Port Logic (EPL), RX and TX.
• Frame Processor (FP)
• Switch Element Data Path (SEDP)
• Switch Element Scheduler (SES)
• Management (MGMT)
This partitioning was designed specifically to attain high throughput,
high port density, low latency, and low power in a single integrated
device.
Figure 4.
FM2112 Block Diagram
15