FBFM2112F897CSLJLS View Datasheet(PDF) - Intel
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FBFM2112F897CSLJLS Datasheet PDF : 169 Pages
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Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
3.1.2
Figure 5.
Ethernet Port Logic Functional Blocks
SerDes
{Registers described in Table 130 through Table 144.}
Eight of the twenty four ports (port numbers 1 - 8) contain a block of
four SerDes and the remaining sixteen ports (port numbers 9 - 24)
contain only a single SerDes. Four pairs of independent high-speed
clock sources, each of which can operate at any rate from 100 MHz to
400 MHz, may independently service four groups of interfaces, as
shown in Table 1. Each of the 24 ports can independently select from
among the two clock inputs routed to it by setting the corresponding bit
in the PORT_CLK_SEL register (Table 46). Since both the serializer and
deserializer in a SerDes utilize the same clock, the Tx and Rx sections
of an interface cannot operate at different frequencies.
Table 1.
RCK1AP/N
RCK1BP/N
RCK2AP/N
RCK2BP/N
RCK3AP/N
RCK3BP/N
RCK4AP/N
RCK4BP/N
Reference Clock to Port Correspondence
Ports 1, 3, 5, 7, 9, 11
Ports 2, 4, 6, 8, 10, 12
Ports 13, 15, 17, 19, 21, 23
Ports 14, 16, 18, 20, 22, 24
19
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