FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

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Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

Ethernet Port Logic (EPL)

The Ethernet Port Logic (EPL) is the per-port replicated block. It is

purposely designed to be as “thin” as possible to enable the FM2112 to

scale -- practically -- to 24 ports. The EPL contains only the essential

features to identify a packet and its header, parse the information

appropriately, and stream the information to the correct location. The

EPL implements the PMA and PCS layers, and it further checks each

frame for various errors, including length and frame errors. The packet

data is buffered into a 64-byte segment for streaming into the switch

element at the Nexus data rate (30 Gb/s per port), beyond which the

EPL is purely cut-through. The header is parsed and sent to the frame

processor. On TX, the EPL collects tag information from the scheduler

and uses that to perform VLAN egress tagging.

Frame Processor (FP)

The Frame Processor (FP) is a centralized and highly-optimized pipeline

that implements all of the complex frame relay policy and congestion

management functions, and keeps statistics for activity across the

entire chip. Once a reservation has been set, the frame processor

pipeline is deterministic, producing one header per clock, and no

further queuing is required. It takes a header as its input and produces

a forwarding mask 6 clocks later - at full line rate for up to 24 ports. It

processes the destination MAC address, source MAC address, VLAN,

and Spanning Tree protocol. In addition, it checks security and

reserved traps, and updates the MAC Address table. It receives queue

status from the switch element scheduler and determines whether to

discard frames or pause inputs on a frame's ingress. And finally it

manages the link aggregation groups.

Switch Element Data Path (SEDP)

The switch element is a fully-provisioned, centrally-buffered switch with

ideal transfer characteristics. It consists of the switch element datapath

and scheduler.

The Switch Element Data Path (SEDP) is a shared memory structure

constructed from Intel's proprietary crossbar and memory technology.

The memory delivers approximately three-quarters Tb/s of bandwidth,

necessary to support sustained transfer of the worst segment corner

case of 65-byte frames. Though it uses crossbars it is not a “crossbar-

based” switch; it is centrally buffered. On ingress, frames are streamed

in from the 24 EPLs through a crossbar, in a non-blocking fashion, to 16

banks of 64 kB of memory (1 MB total), where they are kept while the

headers are queued and scheduled. Each 64-byte segment from the

EPL is striped across the 16 32-bit banks of memory (512 bits at a

time). Another crossbar then connects the 16 banks of memory back

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