FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

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Description

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FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.6.4

Frame Handler Clock

The frame handler clock controls the rate at which frame headers are

processed in the frame handler block. Frame headers are processed

one header per clock cycle, so if the aggregated 24-port frame

throughput is desired to be 300 million frames per second, the frame

handler clock must be set at 300 MHz. The aggregate frame rate for all

ports in frames per second (FPS) should never exceed the frame

handler clock speed in Herz (Hz) or unpredicted behavior will result.

The frame handler clock is generated by an internal PLL using the

FH_PLL_REFCLK clock input pin as its input. The relationship between

the input frequency and the PLL output frequency to the frame handler

is controlled by parameters input in the PLL_FH_CTRL register (See

Table 43). A simplified schematic of the PLL circuit is shown that will

clarify the meaning of the input parameters.

Note:

Figure 21. Frame Handler Clock Generation

The resulting equation governing the PLL output is:

PLL_OUT = FH_REFCLK x M/NP

Where:

• N ==> 1 to 16

• M ==> 4 to 128

• 150 MHz < FVCO (point A) < 650 MHz

• 12.5 MHz < PLL output < 360 MHz

• 1.2 MHz < FH_PLL_REFCLK < 70 MHz

See Table 44 for examples of N, M, and P settings.

72

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