FBFM2112F897CSLJLS View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
FBFM2112F897CSLJLS Datasheet PDF : 169 Pages
| |||
Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
Table 28. Global Register List (Continued)
CLK_MULT_1
FRAME_TIME_OUT
VPD
PLL_FH_CTRL
PLL_FH_STAT
PORT_CLK_SEL
Global
Global
Global
Global
Global
Global
Clock multiples between the CPU
interface, LED interface, and SPI
interface
Configures whether (and how)
frames time out
Vital Product Data
Frame Handler PLL Control
Frame Handler PLL Status
Selects between 2 CML clocks per
port
0x00302
0x00303
0x00304
0x00315
0x00316
0x00317
Table 29. Switch Configuration Register List
Switch Configuration Registers
Name
INTERRUPT_DETECT
GLOBAL_EPL_INT_DETECT
MGR_IP
MGR_IM
FRAME_CTRL_IP
FRAME_CTRL_IM
PERR_IP
PERR_IM
PERR_DEBUG
TRIGGER_IP
TRIGGER_IM
PORT_MAC_SEC_IP
PORT_MAC_SEC_IM
PORT_VLAN_IP_1
PORT_VLAN_IM_1
PORT_VLAN_IP_2
PORT_VLAN_IM_2
SYS_CFG_1
SYS_CFG_2
SYS_CFG_3
SYS_CFG_4
SYS_CFG_6
SYS_CFG_7
Reset
Domain
Global
Global
Global
Global
Global
Global
Global
Global
Global
FH
FH
FH
FH
FH
FH
FH
FH
Mgmt
Global
Global
Global
Global
Description
Address
Detects an interrupt
Detects an interrupt on a port
Chip interrupt pending
Chip interrupt mask
Frame control interrupt pending
Frame control interrupt mask
Parity error interrupt pending
Parity error interrupt mask
Parity error debug
Trigger interrupt pending
Trigger interrupt mask
MAC security interrupt pending
MAC security interrupt mask
VLAN violation interrupt pending
VLAN violation interrupt mask
VLAN violation interrupt pending
VLAN violation interrupt mask
General feature configuration
General feature configuration in the
asynchronous logic
Most significant bit of the CPU’s MAC
address (Port 0)
Least significant bit of the CPU’s MAC
address (Port 0)
Ether-type Trap
Age time
0x00309
0x0030A
0x0030B
0x0030C
0x0030D
0x0030E
0x00312
0x00313
0x00314
0x640C6
0x640C7
0x640C4
0x640C5
0x640C0
0x640C1
0x640C2
0x640C3
0x60001
0x58121
0x60002
0x60003
0x60004
0x0030F
80
Share Link: 