FBFM2112F897CSLJLS View Datasheet(PDF) - Intel
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FBFM2112F897CSLJLS Datasheet PDF : 169 Pages
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Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
5.0
5.1
Note:
5.2
Note:
Register Definitions
This section provides information on the registers used in the FM2112.
Although the registers are generally directly accessible, it is
recommended that they be accessed through the Intel® API where
related registers can be rationally configured as a group in the context
of the application.
Register Conventions
Registers follow these conventions:
• All registers are 32 bits in length
• Tables may be more than 32 bits in length
• There are four types of register fields:
— RW - Read / Write
— RO - Read Only
— CR - Clear on Read
— PIN - Pin
• Registers are located on different reset domains and are reset to their default value
only when their respective domain is reset. The reset domains are:
— Global Reset Domain: Reset only when CHIP_RESET_N is asserted
— Ethernet Port Logic Reset Domain: Reset when CHIP_RESET_N is asserted or
the port reset is active (see PORT_RESET register)
— Frame Handler Reset Domain: Reset when frame handler reset is asserted (see
SOFT_RESET register)
The entries in the MAC address (MA), VLAN Information Database (VID), Forwarding
Information Database (FID), and Management Information Base (MIB) tables are
larger than 32 bits, as follows: MA: 95 bits; VID: 64 bits; FID: 50 bits; MIB: 64 bits.
the Intel®Ethernet Switch Family supports atomic access to these addresses. A read or
write to the MAC address, VLAN, or Flooding ID tables, or the read of a MIB counter is
atomic.
Register Map
The statistics register map is detailed in section 5.7.
Table 28. Global Register List
Global Registers
Name
BOOT_STATUS
SOFT_RESET
PORT_RESET
CHIP_MODE
Reset
Domain
Global
Global
Global
Global
Description
Boot status
Reset switch by software
Reset port by software
Configures various chip-level modes
Address
0x00000
0x00300
0x00318
0x00301
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