FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

4.3.2

Note:

Table 27. CPU Interface Timing Constraints (Continued)

Hold time for ADDR and DATA(in) to

Th2

rising edge of clock

0.5

-

-

ns

-

Output valid for DTACK_N and

Tov

DATA(out) to rising edge of clock

0

-

4.5

ns

Notes

• DTACK_INV, RW_N_INV, SYNC_MODE are static signals. They must be stable before RESET_N is de-

asserted.

• BUSIF_RESET and INTR are asynchronous signals.

• Typical latency to access an internal 32-bit register is in the range of 100-150ns

JTAG Interface

The JTAG interface follows standard timing as defined in the IEEE

1149.1 Standard Test Access Port and Boundary-Scan Architecture,

2001.

When not using the JTAG interface, either drive the TCK pin with an external clock, or

drive the TRST_N pin low. Conversely, when using the JTAG interface assert TRST_N

along with chip reset to ensure proper reset of the JTAG interface prior to use.

78

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