AT91SAM9G46B-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT91SAM9G46B-CU

SMART ARM-based Embedded MPU

Atmel Corporation 

11.4.2.2 NRST External Reset Control

The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out”

signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion

duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate

duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the

NRST pulse.

This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is

driven low for a time compliant with potential external devices connected on the system reset.

As the field is within RSTC_MR, which is backed up, this field can be used to shape the system power-up reset for

devices requiring a longer startup time than the Slow Clock Oscillator.

11.4.3 BMS Sampling

The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is

sampled three slow clock cycles after the Core Power-On Reset output rising edge.

Figure 11-3. BMS Sampling

SLCK

Core Supply

POR output

BMS Signal

proc_nreset

XXX

BMS sampling delay

= 3 cycles

H or L

11.4.4 Reset States

The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports

the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is

performed when the processor reset is released.

SAM9G46 Series [DATASHEET]

75

Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15

Share Link: