AT91SAM9G46B-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT91SAM9G46B-CU

SMART ARM-based Embedded MPU

Atmel Corporation 

11.4.4.1 General Reset

A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises

and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure

the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply

with the Slow Clock Oscillator startup time.

After this time, the processor clock is released at Slow Clock and all the other signals remain valid for three cycles

for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR

reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as

ERSTL defaults at value 0x0.

When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if

the Main Supply POR Cell does not report a Main Supply shutdown.

VDDBU only activates the backup_nreset signal.

The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR

output).

Figure 11-4 shows how the General Reset affects the reset signals.

Figure 11-4. General Reset State

SLCK

MCK

Backup Supply

POR output

Main Supply

POR output

backup_nreset

proc_nreset

RSTTYP

periph_nreset

Startup Time

XXX

Any

Freq.

Processor Startup

= 3 cycles

0x0 = General Reset

XXX

NRST

(nrst_out)

BMS Sampling

EXTERNAL RESET LENGTH

= 2 cycles

76 SAM9G46 Series [DATASHEET]

Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15

Share Link: