AT91SAM9G46B-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT91SAM9G46B-CU

SMART ARM-based Embedded MPU

Atmel Corporation 

11.4.4.5 Watchdog Reset

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts three Slow Clock cycles.

When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:

 If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also

asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST

does not result in a User Reset state.

 If WDRPROC = 1, only the processor reset is asserted.

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if

WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by

default and with a period set to a maximum.

When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.

Figure 11-8. Watchdog Reset

SLCK

MCK

Any

Freq.

wd_fault

proc_nreset

RSTTYP

Any

periph_nreset

Only if

WDRPROC = 0

NRST

(nrst_out)

Processor Startup

= 3 cycles

XXX

0x2 = Watchdog Reset

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

80 SAM9G46 Series [DATASHEET]

Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15

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