STM8S007C8
Electrical characteristics
Figure 8. fCPUmax versus VDD
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Table 17. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Typ
Max Unit
tVDD
tTEMP
VDD rise time rate
VDD fall time rate
Reset releaseï€
delay
-
-
VDD rising
2(1)
-
2(1)
-
ï‚¥
µs/V
ï‚¥
-
-
1.7(1) ms
VIT+
Power-on reset
threshold(2)
-
2.65
2.8
2.95 V
VIT-
Brown-out reset
threshold
-
2.58
2.73
2.88 V
VHYS(BOR)
Brown-out reset
hysteresis
-
-
70
-
mV
1. Guaranteed by design, not tested in production.
2. If VDD is below 2.95 V, the code execution is guaranteed above the VIT- and VIT+ thresholds. RAM content
is kept. The EEPROM programming sequence must not be initiated.
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