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PIC16F1503-IST View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC16F1503-IST
Microchip
Microchip Technology 
PIC16F1503-IST Datasheet PDF : 352 Pages
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FIGURE 28-11: CLC PROPAGATION TIMING
PIC16(L)F1503
Rev. 10-000031A
7/30/2013
CLCxINn
CLC
Input time
LCx_in[n](1)
CLC
Module
LCx_out(1)
CLC
Output time
CLCx
CLCxINn
CLC
Input time
LCx_in[n](1)
CLC
Module
CLC01
CLC02
LCx_out(1)
CLC
Output time
CLC03
CLCx
Note 1: See FIGURE 23-1:, Configurable Logic Cell Block Diagram, to identify specific CLC signals.
TABLE 28-12: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min. Typ† Max. Units Conditions
CLC01* TCLCIN CLC input time
—7
— ns
CLC02* TCLC
CLC module input to output propagation time — 24
— 12
— ns VDD = 1.8V
— ns VDD > 3.6V
CLC03* TCLCOUT CLC output time
Rise Time — OS18 — — (Note 1)
Fall Time — OS19 — — (Note 1)
CLC04* FCLCMAX CLC maximum switching frequency
— 45 — MHz
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:See Table 28-9 for OS18 and OS19 rise and fall times.
2011-2015 Microchip Technology Inc.
DS40001607D-page 283

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