PIC16(L)F1503
TABLE 28-14: ADC CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
AD130* TAD ADC Clock Period (TADC)
1.0
—
6.0 s FOSC-based
ADC Internal FRC Oscillator Period (TFRC) 1.0
2.0
6.0 s ADCS<2:0> = x11 (ADC FRC mode)
AD131 TCNV Conversion Time
(not including Acquisition Time)(1)
—
11
— TAD Set GO/DONE bit to conversion
complete
AD132* TACQ Acquisition Time
—
5.0
— s
AD133* THCD Holding Capacitor Disconnect Time
—
1/2 TAD
—
— 1/2 TAD + 1TCY —
FOSC-based
ADCS<2:0> = x11 (ADC FRC mode)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
TABLE 28-15: COMPARATOR SPECIFICATIONS(1)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
No.
Sym.
Characteristics
Min. Typ. Max. Units
Comments
CM01
VIOFF Input Offset Voltage
—
±7.5
±60
mV CxSP = 1,
VICM = VDD/2
CM02
VICM
Input Common Mode Voltage
0
—
VDD
V
CM03
CMRR Common Mode Rejection Ration
—
50
—
dB
CM04A
Response Time Rising Edge
—
400
800
ns CxSP = 1
CM04B
CM04C
CM04D
CM05*
TRESP(2)
TMC2OV
Response Time Falling Edge
Response Time Rising Edge
Response Time Falling Edge
Comparator Mode Change to
Output Valid
—
200
400
ns CxSP = 1
—
1200
—
ns CxSP = 0
—
550
—
ns CxSP = 0
—
—
10
s
CM06
*
Note 1:
2:
CHYSTER Comparator Hysteresis
—
25
—
mV CxHYS = 1,
CxSP = 1
These parameters are characterized but not tested.
See Section 29.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to
VDD.
DS40001607D-page 286
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