PIC16(L)F1503
TABLE 28-17: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Typ† Max. Units Conditions
SP70* TSSL2SCH, SS to SCK or SCK input
TSSL2SCL
2.25 TCY
— — ns
SP71* TSCH
SCK input high time (Slave mode) 1 TCY + 20 — — ns
SP72* TSCL
SCK input low time (Slave mode)
1 TCY + 20 —
SP73* TDIV2SCH, Setup time of SDI data input to SCK
100
—
TDIV2SCL edge
— ns
— ns
SP74* TSCH2DIL, Hold time of SDI data input to SCK
100
TSCL2DIL edge
— — ns
SP75* TDOR
SP76* TDOF
SDO data output rise time
SDO data output fall time
—
10 25 ns 3.0V VDD 5.5V
—
25 50 ns 1.8V VDD 5.5V
—
10 25 ns
SP77* TSSH2DOZ SS to SDO output high-impedance
10
— 50 ns
SP78* TSCR
SP79* TSCF
SCK output rise time
—
(Master mode)
—
SCK output fall time (Master mode)
—
10 25 ns 3.0V VDD 5.5V
25 50 ns 1.8V VDD 5.5V
10 25 ns
SP80* TSCH2DOV, SDO data output valid after SCK
TSCL2DOV edge
SP81* TDOV2SCH, SDO data output setup to SCK edge
TDOV2SCL
—
—
1 Tcy
— 50 ns 3.0V VDD 5.5V
— 145 ns 1.8V VDD 5.5V
— — ns
SP82* TSSL2DOV SDO data output valid after SS
edge
—
— 50 ns
SP83* TSCH2SSH, SS after SCK edge
TSCL2SSH
1.5 TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS40001607D-page 290
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