PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 20-4: PMDOUT: PARALLEL PORT OUTPUT DATA REGISTER

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

31:24

23:16

15:8

7:0

U-0

—

U-0

—

R/W-0

R/W-0

U-0

—

U-0

—

R/W-0

R/W-0

U-0

—

U-0

—

R/W-0

R/W-0

U-0

U-0

—

—

U-0

U-0

—

—

R/W-0

R/W-0

DATAOUT<15:8>

R/W-0

R/W-0

DATAOUT<7:0>

U-0

—

U-0

—

R/W-0

R/W-0

Bit

25/17/9/1

U-0

—

U-0

—

R/W-0

R/W-0

Bit

24/16/8/0

U-0

—

U-0

—

R/W-0

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 DATAOUT<15:0>: Port Data Output bits

This register is used for Read operations in the Enhanced Parallel Slave mode and Write operations for Dual

Buffer Master mode.

In Dual Buffer Master mode, the DUALBUF bit (PMPCON<17>) = 1, a write to the MSB triggers the trans-

action on the PMP port. When MODE16 = 1, MSB = DATAOUT<15:8>. When MODE16 = 0,

MSB = DATAOUT<7:0>.

Note: In Master mode, a read will return the last value written to the register. In Slave mode, a read will return

indeterminate results.

REGISTER 20-5: PMDIN: PARALLEL PORT INPUT DATA REGISTER

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

31:24

23:16

15:8

7:0

U-0

—

U-0

—

R/W-0

R/W-0

U-0

—

U-0

—

R/W-0

R/W-0

U-0

—

U-0

—

R/W-0

R/W-0

U-0

U-0

—

—

U-0

U-0

—

—

R/W-0

R/W-0

DATAIN<15:8>

R/W-0

R/W-0

DATAIN<7:0>

U-0

—

U-0

—

R/W-0

R/W-0

Bit

25/17/9/1

U-0

—

U-0

—

R/W-0

R/W-0

Bit

24/16/8/0

U-0

—

U-0

—

R/W-0

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 DATAIN<15:0>: Port Data Input bits

This register is used for both Parallel Master Port mode and Enhanced Parallel Slave mode.

In Parallel Master mode, a write to the MSB triggers the write transaction on the PMP port. Similarly, a read

to the MSB triggers the read transaction on the PMP port.

When MODE16 = 1, MSB = DATAIN<15:8>. When MODE16 = 0, MSB = DATAIN<7:0>.

Note: This register is not used in Dual Buffer Master mode (i.e., DUALBUF bit (PMPCON<17>) = 1).

DS60001290E-page 214

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