6.1 Control Registers
TABLE 6-1: FLASH CONTROLLER REGISTER MAP
Bits
31/15
30/14
29/13 28/12
27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F400
NVMCON(1)
31:16
15:0
—
WR
—
—
—
—
—
WREN WRERR LVDERR LVDSTAT —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NVMOP<3:0>
— 0000
0000
F410
NVMKEY
31:16
15:0
NVMKEY<31:0>
0000
0000
F420
NVMADDR(1)
31:16
15:0
NVMADDR<31:0>
0000
0000
F430
NVMDATA
31:16
15:0
NVMDATA<31:0>
0000
0000
F440
NVMSRC
ADDR
31:16
15:0
NVMSRCADDR<31:0>
0000
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for more
information.