PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC32MX230F128L-I/PF
Microchip Technology
PIC32MX230F128L-I/PF Datasheet PDF : 382 Pages
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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
REGISTER 6-4: NVMDATA: FLASH PROGRAM DATA REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
R/W-0
R/W-0
R/W-0
R/W-0
Bit
30/22/14/6
R/W-0
R/W-0
R/W-0
R/W-0
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
NVMDATA<31:24>
R/W-0
R/W-0
NVMDATA<23:16>
R/W-0
R/W-0
NVMDATA<15:8>
R/W-0
R/W-0
NVMDATA<7:0>
Bit
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 NVMDATA<31:0>: Flash Programming Data bits
Note: The bits in this register are only reset by a Power-on Reset (POR).
REGISTER 6-5: NVMSRCADDR: SOURCE DATA ADDRESS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31:24
23:16
15:8
7:0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADDR<31:24>
R/W-0
R/W-0
NVMSRCADDR<23:16>
R/W-0
R/W-0
NVMSRCADDR<15:8>
R/W-0
R/W-0
NVMSRCADDR<7:0>
R/W-0
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0
NVMSRCADDR<31:0>: Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits
(NVMCON<3:0>) are set to perform row programming.
2014-2017 Microchip Technology Inc.
DS60001290E-page 67
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