PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC32MX230F128L-I/PF
Microchip Technology
PIC32MX230F128L-I/PF Datasheet PDF : 382 Pages
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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
REGISTER 6-2: NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
W-0
W-0
W-0
W-0
Bit
30/22/14/6
W-0
W-0
W-0
W-0
Bit
29/21/13/5
W-0
W-0
W-0
W-0
Bit
Bit
28/20/12/4 27/19/11/3
W-0
W-0
NVMKEY<31:24>
W-0
W-0
NVMKEY<23:16>
W-0
W-0
NVMKEY<15:8>
W-0
W-0
NVMKEY<7:0>
Bit
26/18/10/2
W-0
W-0
W-0
W-0
Bit
25/17/9/1
W-0
W-0
W-0
W-0
Bit
24/16/8/0
W-0
W-0
W-0
W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 NVMKEY<31:0>: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read.
Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
REGISTER 6-3: NVMADDR: FLASH ADDRESS REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
R/W-0
R/W-0
R/W-0
R/W-0
Bit
30/22/14/6
R/W-0
R/W-0
R/W-0
R/W-0
Bit
29/21/13/5
R/W-0
R/W-0
R/W-0
R/W-0
Bit
Bit
28/20/12/4 27/19/11/3
R/W-0
R/W-0
NVMADDR<31:24>
R/W-0
R/W-0
NVMADDR<23:16>
R/W-0
R/W-0
NVMADDR<15:8>
R/W-0
R/W-0
NVMADDR<7:0>
Bit
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0
NVMADDR<31:0>: Flash Address bits
Bulk/Chip/PFM Erase: Address is ignored
Page Erase: Address identifies the page to erase
Row Program: Address identifies the row to program
Word Program: Address identifies the word to program
DS60001290E-page 66
2014-2017 Microchip Technology Inc.
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