STLC5460
INPUT PCM OFFSET REGISTER (IPOF)
7
IOF9
IOF8
IOF7
IOF6
IOF5
After Reset 00 (H)
IOF 4
IOF3
0
IOF 2
IOF9/2
Input PCM Offset 9 to 2.
Associated with IOF1/0, these ten bits indicate the delay between PFS signal and the
first bit of the frame, for each input
OUTPUT PCM OFFSET REGISTER (OPOF)
7
OOF9
OOF8
OOF7
OOF6
IOF5
After Reset 00 (H)
OOF 4
OOF3
0
OOF 2
OOF9/2
Output PCM Offset 9 to 2.
Associated with OOF1/0 of complementary offset register, these ten bits indicate the
delay between bit 0 of the frame out going versus bit 0 of the frame incoming.
INPUT PCM SHIFT 1 (IPSH1)
7
0
0
P1SH2 P1SH1 P1SH0
0
P0SH2 P0SH1 P0SH0
After Reset 00 (H)
P1SH2/0
PCM1 Shift 2 to 0.
This number (0 to 7) is added to Input PCM offset to obtain the total shift of the frame of
PCM1.
P0SH2/0
PCM0 shift 2 to 0.
This number (0 to 7) is added to Input PCM offset to obtain the total shift of the frame of
PCM0.
INPUT PCM SHIFT 2 (IPSH2)
7
0
0
P3SH2 P3SH1 P3SH0
0
P2SH2 P2SH1 P2SH0
After Reset 00 (H)
P3SH2/0
PCM3 Shift 2 to 0.
This number (0 to 7) is added to Input PCM offset to obtain the total shift of the frame of
PCM3.
P2SH2/0
PCM2 Shift 2 to 0.
This number (0 to 7) is added to Input PCM offset to obtain the total shift of the frame of
PCM2.
OUTPUT PCM SHIFT 1 (OPSH1)
7
P1E
P1SH2 P1SH1 P1SH0
P0E
After Reset 00 (H)
P1E
Output PCM1 Enable.
P1E = 0. PCM1 output is at high impedance.
P1E = 1. PCM1 output is enable.
P0SH2
P0SH1
0
P0SH0
16/54