STLC5460 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5460 Datasheet PDF : 54 Pages
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STLC5460
FIRST CASE CM = 1: ACCESS TO COMMAND MEMORY
R/W
CM
CR5
CR4
CR3
CR2
CR1
CR0
R/W
1
CH1
CH0
SS1
SS0
DS1
DS0
After Reset 00 (H)
Read/Write
R/W = 0 (Write). The eight bits of Source Register and the six lower bits of this
Command Register are loaded into the Command Memory (14 bits). The Address bits
are given by the Destination Register (8 bits). Write cycle starts when Destination
Register is loaded by the microprocessor.
CH0/1
R/W = 1 (Read).
The 14 bits of Command memory addressed by the Destination Register are loaded
respectively into Command Register (6 bits) and Source Register (8 bits). Read cycle
starts when Destination Register is loaded by the micro-processor.
Channel Data Rate
CH1
CH0
Description
0
0
The output is at high impedance during the time slot selected
0
1
16kb/s subchannel is selected
1
0
32kb/s subchannel is selected
1
1
64kb/s channel is selected
During the time slot selected, the output is at high impedance for the subchannelsnot selected.
SS 0/1
Source Subchannel selected.
Data Rate
16kb/s
32kb/s
SS1
SS0
0
0
0
1
1
0
1
1
0
0
0
1
Bit 7 is trasmitted first.
DS 0/1
Destination Subchannel selected.
Source channel
Bits 6-7
Bits 4-5
Bits 2-3
Bits 0-1
Bits 4 to 5
Bits 0 to 3
Data Rate
16kb/s
32kb/s
Bit 7 is trasmitted first.
SS1
SS0
0
0
0
1
1
0
1
1
0
0
0
1
Source channel
Bits 6-7
Bits 4-5
Bits 2-3
Bits 0-1
Bits 4 to 5
Bits 0 to 3
20/54
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