DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Introduction—Intel® Quark SoC X1000
1.2.12
1.2.13
1.2.14
1.2.15
1.2.16
1.3
• Two I2C speeds supported: Standard (100 Kbit/s) and Fast (400 Kbit/s) data rates
• Fully asynchronous I2C clock signal
• Master I2C operation
GPIO Features
• 16 GPIO pins provided
• 6 GPIO pins remain active during S3 and can be used to wake the system from the
Suspend state.
• Remaining 10 GPIO pins are powered during S0 state only and are not available in
S3
SPI Master Controller
• Two SPI Master controllers
• One Chip Select per master controller
• Configurable SCLK frequency from 1 kHz up to 25 MHz
High Speed UART Controller with DMA
• Two 16550 compliant UART controllers
• Supported Baud rates from 300 to 2764800
• Integrated DMA capability with hardware flow control
Legacy Bridge
The Legacy Bridge is a collection of hardware blocks critical to implement an Intel
Architecture compatible platform. Some of its key features are:
• A 20 MHz Serial Peripheral Interface (SPI) for Flash only - stores boot FW and
system configuration data
• A Power Management Controller (PMC) that controls many of the power
management features present in the SoC
• Legacy Bridge Components - Provides hardware blocks required to support legacy
PC platform features. The legacy bridge components include the RTC, Interrupt
Controllers, Timers and General Purpose I/Os (GPIO).
Package
The SoC is packaged in a Flip-Chip Ball Grid Array (FCBGA) package with 393 solder
balls with 0.593 mm ball pitch. The package dimensions are 15mm x 15mm.
Component Identification
The Intel® Quark SoC X1000 stepping is identified by both:
• Processor Family/Model/Stepping returned by the CPUID instruction. This always
returns 0x590 for SoC.
• Revision ID register of the Host Bridge, located at D0:F0. Reads of the register
reflect the stepping.
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
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