DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Physical Interfaces—Inte® Quark SoC X1000

2.1

Table 4.

Table 5.

Table 6.

2.2

Pin States Through Reset

This chapter describes the each signal state before, during, and directly after reset.

Additionally, some signals have internal pull-up/pull-down termination resistors, and

their values are also provided.

I/O Power Well Definitions

Power Type

CORE

SUS

RTC

Power Well Description

Core I/O, and everything else uses the CORE power well.

Devices outside of memory that must remain on in the S3 state use the SUS power well.

Devices that must be on in the S4/S5 state use the RTC power well.

Buffer Type Definitions

Buffer Type

Buffer Description

PCIe*

PCIe*, differential buffer type

SSTL-15

DDR3, 1.5V tolerant SSTL buffer type

DDI

DDR (TMDS, DP) 1.0V tolerant differential buffer type

CMOS[Voltage]

CMOS buffer type. [Voltage] can be of the following types: 1.05, 1.5, 1.8, and 3.3.

CMOS[Voltage]_OD

Open drain CMOS buffer type [Voltage] can be of the following types: 1.05, 1.5, 1.8 and

3.3.

Analog

Analog pins that do not have specific digital requirements. Often used for circuit

calibration or monitoring.

Default Buffer State Definitions

Buffer State

High-Z

Do Not Care

VOH

VOL

Unknown

VIH

VIL

Pull-up

Pull-down

Running

Off

Description

The SoC places this output in a high-impedance state. For inputs, external drivers are not

expected.

The state of the input (driven or tristated) does not affect the SoC. For outputs, it is

assumed that the output buffer is in a high-impedance state.

The SoC drives this signal high.

The SoC drives this signal low.

The SoC drives or expects an indeterminate value.

The SoC expects/requires the signal to be driven high.

The SoC expects/requires the signal to be driven low.

This signal is pulled high by a pull-up resistor (internal or external — internal value

specified in “Term” column).

This signal is pulled low by a pull-down resistor (internal or external — internal value

specified in “Term” column).

The clock is toggling, or the signal is transitioning.

The power plane for this signal is powered down. The SoC does not drive outputs, and

inputs should not be driven to the SoC. (VSS on output)

System Memory Signals

See Section 6.0 for more details of the DDR3 interface signals. Termination not listed.

October 2013

Document Number: 329676-001US

Inte® Quark SoC X1000

DS

47

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