DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
21.13.6.3Redirection Table Entry Lower (RTE[0-23]L)—Offset 10h - 3Eh ..... 908
21.13.6.4Redirection Table Entry Upper (RTE[0-23]U)—Offset 11h - 3Fh ..... 909
21.14 Watchdog Timer.............................................................................................. 911
21.14.1Features ............................................................................................. 911
21.14.2Use .................................................................................................... 911
21.14.3Register Map ....................................................................................... 912
21.14.4I/O Mapped Registers ........................................................................... 912
21.14.4.1Preload Value 1 Register 0 (PV1R0)—Offset 0h ........................... 913
21.14.4.2Preload Value 1 Register 1 (PV1R1)—Offset 1h ........................... 913
21.14.4.3Preload Value 1 Register 2 (PV1R2)—Offset 2h ........................... 914
21.14.4.4Preload Value 2 Register 0 (PV2R0)—Offset 4h ........................... 914
21.14.4.5Preload Value 2 Register 1 (PV2R1)—Offset 5h ........................... 915
21.14.4.6Preload Value 2 Register 2 (PV2R2)—Offset 6h ........................... 915
21.14.4.7Reload Register 0 (RR0)—Offset Ch ........................................... 915
21.14.4.8Reload Register 1 (RR1)—Offset Dh........................................... 916
21.14.4.9WDT Configuration Register (WDTCR)—Offset 10h ...................... 916
21.14.4.10WDT Lock Register (WDTLR)—Offset 18h ................................. 917
22.0 Debug Port and JTAG/TAP ..................................................................................... 919
22.1 Signal Descriptions .......................................................................................... 919
22.2 Features ........................................................................................................ 920
22.2.1 OpenOCD ............................................................................................ 920
Figures
1 Block Diagram ......................................................................................................... 38
2 Intel® Quark SoC X1000 PCI View.............................................................................. 42
3 Signals In Default System Pin List .............................................................................. 46
4 PCI Express Transmitter Eye...................................................................................... 74
5 PCI Express Receiver Eye .......................................................................................... 75
6 USB Rise and Fall Time ............................................................................................. 77
7 USB Jitter ............................................................................................................... 77
8 USB EOP Width ........................................................................................................ 78
9 SPI Interface Timing................................................................................................. 79
10 SDIO Interface Timing .............................................................................................. 80
11 Measurement Points for Differential Clocks .................................................................. 82
12 Physical Address Space - Low DRAM & MMIO ............................................................... 90
13 Physical Address Space - MMIO.................................................................................. 91
14 Physical Address Space - DOS DRAM .......................................................................... 92
15 Physical Address Space - SMM Range ......................................................................... 93
16 Bus 0 PCI Devices and Functions................................................................................ 96
17 Message Bus with PCI Space ..................................................................................... 97
18 SoC Platform Clocking ............................................................................................ 100
19 RTC Power Well Timing Diagrams ............................................................................. 111
20 Power-Up Sequence without G2/G3 .......................................................................... 112
21 Power Up Sequence................................................................................................ 114
22 eSRAM 4KB Page Mapping....................................................................................... 124
23 eSRAM 512KB Page Mapping ................................................................................... 125
24 Intel® Quark SoC X1000 Host Bridge Register Map ..................................................... 128
25 Register Map ......................................................................................................... 236
26 PCI Express Register Map........................................................................................ 262
27 Ethernet Register Map ............................................................................................ 309
28 USB Register Map .................................................................................................. 423
29 SD Memory Card Bus Topology ................................................................................ 579
30 SDIO Card Bus Topology ......................................................................................... 579
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
31
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