DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—

82 10/100 Ethernet Interface Signals ............................................................................ 307

83 Summary of PCI Configuration Registers—0/20/6 ....................................................... 309

84 Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 325

85 Signals.................................................................................................................. 421

86 Summary of PCI Configuration Registers—0/20/2 ....................................................... 423

87 Summary of PCI Configuration Registers—0/20/3 ....................................................... 439

88 Summary of PCI Configuration Registers—0/20/4 ....................................................... 457

89 Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 472

90 Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 535

91 Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 555

92 SDIO/SD/eMMC Interface Signals ............................................................................. 577

93 SDIO/SD/eMMC Features......................................................................................... 578

94 Summary of PCI Configuration Registers—0/20/0 ....................................................... 582

95 Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 598

96 UART 0 Interface Signals ......................................................................................... 649

97 UART 1 Interface Signals ......................................................................................... 649

98 Baud Rates Achievable with Different DLAB Settings.................................................... 650

99 Summary of PCI Configuration Registers—0/20/1 ....................................................... 655

100 Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 670

101 Summary of Memory Mapped I/O Registers—BAR1 ..................................................... 680

102 I2C* Signals .......................................................................................................... 717

103 I2C* Definition of Bits in First Byte............................................................................ 720

104 GPIO Signals ......................................................................................................... 724

105 Summary of PCI Configuration Registers—0/21/2 ....................................................... 725

106 Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 741

107 Summary of Memory Mapped I/O Registers—BAR1 ..................................................... 763

108 SPI Interface Signals .............................................................................................. 773

109 SPI Clock Frequency Settings ................................................................................... 776

110 Summary of PCI Configuration Registers—0/21/0 ....................................................... 778

111 Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 793

112 Summary of PCI Configuration Registers—0/31/0 ....................................................... 803

113 Summary of Memory Mapped I/O Registers—RCBA ..................................................... 813

114 Summary of I/O Registers ....................................................................................... 818

115 Summary of I/O Registers—GPE0BLK ........................................................................ 821

116 Summary of I/O Registers—PM1BLK ......................................................................... 827

117 Legacy GPIO Signals ............................................................................................... 831

118 Summary of I/O Registers—GBA............................................................................... 832

119 Legacy SPI Signals ................................................................................................. 841

120 Summary of Memory Mapped I/O Registers—RCBA ..................................................... 843

121 Counter Operating Modes ........................................................................................ 859

122 Register Aliases...................................................................................................... 861

123 8254 Interrupt Mapping .......................................................................................... 867

124 Summary of Memory Mapped I/O Registers—0xFED00000 ........................................... 868

125 RTC Signals ........................................................................................................... 878

126 I/O Registers Alias Locations .................................................................................... 880

127 Indexed Registers................................................................................................... 880

128 IRQAGENT Description ............................................................................................ 884

129 Interrupt Controller Connections............................................................................... 885

130 Interrupt Status Registers ....................................................................................... 886

131 Content of Interrupt Vector Byte............................................................................... 886

132 8259 I/O Registers Alias Locations ............................................................................ 892

133 Summary of I/O Registers ....................................................................................... 892

134 I/O APIC Memory Mapped Registers .......................................................................... 906

135 Index Registers ...................................................................................................... 907

136 Summary of I/O Registers—WDTBA .......................................................................... 912

Intel® Quark SoC X1000

DS

34

October 2013

Document Number: 329676-001US

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