DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
| |||
Intel® Quark SoC X1000—Introduction
1.2.7
1.2.8
1.2.9
1.2.10
1.2.11
Ethernet Features
• 10 and 100 Mbps data transfer rates with RMII interface to communicate with an
external Fast Ethernet PHY
• Full-duplex operation:
— IEEE 802.3x flow control support
— Optional forwarding of received pause control frames to the user application
• Half-duplex operation:
— CSMA/CD Protocol support
• Flexible address filtering modes:
— 64-bit Hash filter for multicast and unicast (DA) addresses
— Option to pass all multicast addressed frames
— Promiscuous mode to pass all frames without any filtering for network
monitoring
— Pass all incoming packets (as per filter) with a status report
• Programmable frame length to support Standard Ethernet frames with size up to
1522 bytes
• Enhanced Receive module for checking IPv4 header checksum and TCP, UDP, or
ICMP checksum encapsulated in IPv4 or IPv6 datagrams (Type 2)
• Support Ethernet frame time stamping as described in IEEE 1588-2002 and IEEE
1588-2008. The 64-bit timestamps are given in the transmit or receive status of
each frame.
USB2 Host Controller Features
• 2 host ports that support high-speed (480 Mbps), full-speed (12 Mbps), and low-
speed (1.5 Mbps) operation
• EHCI and OHCI host controllers
USB2 Device Controller Features
• Single device port that supports high-speed (480 Mbps) and full-speed (12 Mbps)
operation
SD/SDIO/eMMC Controller Features
• Host Controller provides a single port configurable as an SD, SDIO, or eMMC
interface
• SD Clock Frequency up to 50 MHz
• Supports SD Host Controller Standard Specification 3.0
• Supports SDIO card specification 3.0
• Supports SD Memory Card Specification 3.0
• Supports SD Memory Card Security Specification 1.01
• Supports eMMC Specification 4.41
I2C* Master Controller
• Two-wire I2C serial bus interface
Intel® Quark SoC X1000
DS
40
October 2013
Document Number: 329676-001US
Share Link: 