DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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Description
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
17.6
17.5.12Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch....................... 589
17.5.13Subsystem ID (SUB_SYS_ID)—Offset 2Eh ............................................... 589
17.5.14Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h.............. 589
17.5.15Capabilities Pointer (CAP_POINTER)—Offset 34h....................................... 590
17.5.16Interrupt Line Register (INTR_LINE)—Offset 3Ch ...................................... 590
17.5.17Interrupt Pin Register (INTR_PIN)—Offset 3Dh ......................................... 591
17.5.18MIN_GNT (MIN_GNT)—Offset 3Eh .......................................................... 591
17.5.19MAX_LAT (MAX_LAT)—Offset 3Fh ........................................................... 591
17.5.20Capability ID (PM_CAP_ID)—Offset 80h................................................... 592
17.5.21Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ........................... 592
17.5.22Power Management Capabilities (PMC)—Offset 82h ................................... 592
17.5.23Power Management Control/Status Register (PMCSR)—Offset 84h .............. 593
17.5.24PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h ..... 594
17.5.25Power Management Data Register (DATA_REGISTER)—Offset 87h .............. 594
17.5.26Capability ID (MSI_CAP_ID)—Offset A0h ................................................. 595
17.5.27Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h .......................... 595
17.5.28Message Control (MESSAGE_CTRL)—Offset A2h ....................................... 595
17.5.29Message Address (MESSAGE_ADDR)—Offset A4h ..................................... 596
17.5.30Message Data (MESSAGE_DATA)—Offset A8h .......................................... 596
17.5.31Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ...................................... 597
17.5.32Pending Bits for MSI (PER_VEC_PEND)—Offset B0h .................................. 597
Memory Mapped Registers................................................................................ 598
17.6.1 SDMA System Address Register (SYS_ADR)—Offset 0h.............................. 599
17.6.2 Block Size Register (BLK_SIZE)—Offset 4h .............................................. 600
17.6.3 Block Count Register (BLK_COUNT)—Offset 6h......................................... 601
17.6.4 Argument Register (ARGUMENT)—Offset 8h............................................. 602
17.6.5 Transfer Mode Register (TX_MODE)—Offset Ch......................................... 602
17.6.6 Command Register (CMD)—Offset Eh...................................................... 604
17.6.7 Response Register 0 (RESPONSE0)—Offset 10h........................................ 605
17.6.8 Response Register 2 (RESPONSE2)—Offset 14h........................................ 606
17.6.9 Response Register 4 (RESPONSE4)—Offset 18h........................................ 606
17.6.10Response Register 6 (RESPONSE6)—Offset 1Ch........................................ 607
17.6.11Buffer Data Port Register (BUF_DATA_PORT)—Offset 20h .......................... 607
17.6.12Present State Register (PRE_STATE)—Offset 24h...................................... 608
17.6.13Host Control Register (HOST_CTL)—Offset 28h ........................................ 612
17.6.14Power Control Register (PWR_CTL)—Offset 29h ........................................ 613
17.6.15Block Gap Control Register (BLK_GAP_CTL)—Offset 2Ah ............................ 613
17.6.16Wakeup Control Register (WAKEUP_CTL)—Offset 2Bh ............................... 615
17.6.17Clock Control Register (CLK_CTL)—Offset 2Ch.......................................... 616
17.6.18Timeout Control Register (TIMEOUT_CTL)—Offset 2Eh .............................. 618
17.6.19Software Reset Register (SW_RST)—Offset 2Fh........................................ 619
17.6.20Normal Interrupt Status Register (NML_INT_STATUS)—Offset 30h.............. 620
17.6.21Error Interrupt Status Register (ERR_INT_STATUS)—Offset 32h ................. 622
17.6.22Normal Interrupt Status Enable (NRM_INT_STATUS_EN)—Offset 34h .......... 624
17.6.23Error Interrupt Status Enable Register (ERR_INT_STAT_EN)—Offset 36h ..... 625
17.6.24Normal Interrupt Signal Enable Register (NRM_INT_SIG_EN)—Offset 38h .... 626
17.6.25Error Interrupt Signal Enable Register (ERR_INT_SIG_EN)—Offset 3Ah........ 628
17.6.26Auto CMD12 Error Status Register (CMD12_ERR_STAT)—Offset 3Ch ........... 629
17.6.27Host Control 2 Register (HOST_CTRL_2)—Offset 3Eh ................................ 630
17.6.28Capabilities Register (CAPABILITIES)—Offset 40h ..................................... 631
17.6.29Capabilities Register 2 (CAPABILITIES_2)—Offset 44h ............................... 633
17.6.30Maximum Current Capabilities Register (MAX_CUR_CAP)—Offset 48h .......... 634
17.6.31Force Event Register for Auto CMD12 Error Status
(FORCE_EVENT_CMD12_ERR_STAT)—Offset 50h...................................... 635
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
21
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