DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
20.5
20.4.30Message Data (MESSAGE_DATA)—Offset A8h .......................................... 791
20.4.31Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ...................................... 792
20.4.32Pending Bits for MSI (PER_VEC_PEND)—Offset B0h .................................. 792
Memory Mapped Registers................................................................................ 793
20.5.1 SPI Control Register 0 (SSCR0)—Offset 0h .............................................. 793
20.5.2 SPI Control Register 1 (SSCR1)—Offset 4h .............................................. 794
20.5.3 SPI Status Register (SSSR)—Offset 8h .................................................... 796
20.5.4 SPI Data Register (SSDR)—Offset 10h .................................................... 797
20.5.5 DDS Clock Rate Register (DDS_RATE)—Offset 28h.................................... 798
21.0 Legacy Bridge........................................................................................................ 801
21.1 Features ........................................................................................................ 801
21.2 Register Map .................................................................................................. 802
21.3 PCI Configuration Registers .............................................................................. 803
21.3.1 PCI Device ID and Vendor ID Fields (PCI_DEVICE_VENDOR)—Offset 0h....... 804
21.3.2 PCI Status and Command Fields (PCI_STATUS_COMMAND)—Offset 4h ........ 804
21.3.3 PCI Class Code and Revision ID Fields (PCI_CLASS_REVISION)—Offset 8h... 805
21.3.4 PCI Miscellaneous Fields (PCI_MISC)—Offset Ch ....................................... 805
21.3.5 PCI Subsystem ID and Subsystem Vendor ID Fields
(PCI_SUBSYSTEM)—Offset 2Ch .............................................................. 806
21.3.6 GPIO Base Address (GBA)—Offset 44h .................................................... 807
21.3.7 PM1_BLK Base Address (PM1BLK)—Offset 48h ......................................... 807
21.3.8 GPE0_BLK Base Address (GPE0BLK)—Offset 4Ch ...................................... 807
21.3.9 ACPI Control (ACTL)—Offset 58h ............................................................ 808
21.3.10PIRQA, PIRQB, PIRQC and PIRQD Routing Control (PABCDRC)—Offset 60h... 808
21.3.11PIRQE, PIRQF, PIRQG and PIRQH Routing Control (PEFGHRC)—Offset 64h ... 810
21.3.12Watch Dog Timer Base Address (WDTBA)—Offset 84h ............................... 810
21.3.13BIOS Decode Enable (BCE)—Offset D4h .................................................. 811
21.3.14BIOS Control (BC)—Offset D8h .............................................................. 812
21.3.15Root Complex Base Address (RCBA)—Offset F0h ...................................... 813
21.4 Memory Mapped Registers................................................................................ 813
21.4.1 Root Complex Register Block ................................................................. 813
21.4.1.1 Root Complex Topology Capabilities List (RCTCL)—Offset 0h......... 814
21.4.1.2 Element Self Description (ESD)—Offset 4h ................................. 814
21.4.1.3 Interrupt Queue Agent 0 (IRQAGENT0)—Offset 3140h ................. 815
21.4.1.4 Interrupt Queue Agent 1 (IRQAGENT1)—Offset 3142h ................. 815
21.4.1.5 Interrupt Queue Agent 2 (IRQAGENT2)—Offset 3144h ................. 816
21.4.1.6 Interrupt Queue Agent 3 (IRQAGENT3)—Offset 3146h ................. 816
21.4.1.7 RTC Configuration (RC)—Offset 3400h ....................................... 817
21.5 IO Registers ................................................................................................... 818
21.5.1 Fixed IO Registers ................................................................................ 818
21.5.1.1 NMI Status and Control Register (NSC)—Offset 61h..................... 818
21.5.1.2 NMI Enable and RTC Index Register (NMIE)—Offset 70h............... 819
21.5.1.3 Software SMI Control Port (SWSMICTL)—Offset B2h .................... 819
21.5.1.4 Software SMI Status Port (SWSMISTS)—Offset B3h..................... 820
21.5.1.5 Reset Control Register (RSTC)—Offset CF9h ............................... 820
21.5.2 ACPI GPE0 Block .................................................................................. 821
21.5.2.1 GPE0 Status Register (GPE0STS)—Offset 0h ............................... 821
21.5.2.2 GPE0 Enable Register (GPE0EN)—Offset 4h ................................ 822
21.5.2.3 SMI Enable Register (SMIEN)—Offset 10h .................................. 822
21.5.2.4 SMI Status Register (SMISTS)—Offset 14h ................................. 824
21.5.2.5 General Purpose Event Control Register (GPEC)—Offset 18h ......... 825
21.5.2.6 Power Management Configuration Core Well Register
(PMCW)—Offset 28h................................................................ 825
21.5.2.7 Power Management Configuration Suspend Well Register (PMSW)—
Offset 2Ch ............................................................................. 826
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
27
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