DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
21.8
21.9
21.7.4.21Prefix Opcode Configuration (PREOP)—Offset 3074h .................... 852
21.7.4.22Opcode Type Configuration (OPTYPE)—Offset 3076h.................... 853
21.7.4.23Opcode Menu Configuration - Lower 32 Bits (OPMENU_1)—Offset
3078h ................................................................................... 853
21.7.4.24Opcode Menu Configuration - Upper 32 Bits (OPMENU_2)—Offset
307Ch ................................................................................... 854
21.7.4.25Protected BIOS Range 0 (PBR0)—Offset 3080h ........................... 855
21.7.4.26Protected BIOS Range 1 (PBR1)—Offset 3084h ........................... 855
21.7.4.27Protected BIOS Range 2 (PBR2)—Offset 3088h ........................... 856
8254 Programmable Interval Timer.................................................................... 858
21.8.1 Features ............................................................................................. 858
21.8.1.1 Counter 0, System Timer ......................................................... 858
21.8.1.2 Counter 1, Refresh Request Signal ............................................ 858
21.8.1.3 Counter 2, Speaker Tone ......................................................... 858
21.8.2 Use .................................................................................................... 858
21.8.2.1 Timer Programming ................................................................ 858
21.8.2.2 Reading from the Interval Timer ............................................... 859
21.8.3 Register Map ....................................................................................... 860
21.8.4 Timer I/O Registers .............................................................................. 861
21.8.4.1 Counter 0 Interval Time Status Byte Format (C0TS)—Offset 40h ... 862
21.8.4.2 Counter 1 Interval Time Status Byte Format (C1TS)—Offset 41h ... 862
21.8.4.3 Counter 2 Interval Time Status Byte Format (C2TS)—Offset 42h ... 863
21.8.4.4 Timer Control Word Register (TCW)—Offset 43h ......................... 864
21.8.4.5 Counter 0 Counter Access Port Register (C0AP)—Offset 50h ......... 864
21.8.4.6 Counter 1 Counter Access Port Register (C1AP)—Offset 51h ......... 865
21.8.4.7 Counter 2 Counter Access Port Register (C2AP)—Offset 52h ......... 865
High Precision Event Timer (HPET)..................................................................... 865
21.9.1 Features ............................................................................................. 866
21.9.1.1 Non-Periodic Mode - All Timers ................................................. 866
21.9.1.2 Periodic Mode - Timer 0 Only.................................................... 866
21.9.1.3 Interrupts .............................................................................. 867
21.9.2 Register Map ....................................................................................... 867
21.9.3 Memory Mapped Registers..................................................................... 868
21.9.3.1 General Capabilities and ID Register - Lower 32 Bits
(GCID_1)—Offset 0h ............................................................... 869
21.9.3.2 General Capabilities and ID Register - Upper 32 Bits
(GCID_2)—Offset 4h ............................................................... 870
21.9.3.3 General Configuration (GC)—Offset 10h ..................................... 870
21.9.3.4 General Interrupt Status Register (GIS)—Offset 20h.................... 870
21.9.3.5 Main Counter Value Register - Lower 32 Bits (MCV_1)—Offset F0h 871
21.9.3.6 Main Counter Value Register - Upper 32 Bits (MCV_2)—Offset F4h 871
21.9.3.7 Timer 0 Config and Capabilities Register - Lower 32 Bits
(T0C_1)—Offset 100h.............................................................. 872
21.9.3.8 Timer 0 Config and Capabilities Register - Upper 32 Bits
(T0C_2)—Offset 104h.............................................................. 873
21.9.3.9 Timer 0 Comparator Value Register - Lower 32 Bits
(T0CV_1)—Offset 108h............................................................ 873
21.9.3.10Timer 0 Comparator Value Register - Upper 32 Bits
(T0CV_2)—Offset 10Ch............................................................ 873
21.9.3.11Timer 1 Config and Capabilities Register - Lower 32 Bits (T1C_1)—
Offset 120h............................................................................ 874
21.9.3.12Timer 1 Config and Capabilities Register - Upper 32 Bits (T1C_2)—
Offset 124h............................................................................ 875
21.9.3.13Timer 1 Comparator Value Register (T1CV_1)—Offset 128h .......... 875
21.9.3.14Timer 2 Config and Capabilities Register - Lower 32 Bits (T2C_1)—
Offset 140h............................................................................ 875
21.9.3.15Timer 2 Config and Capabilities Register - Upper 32 Bits (T2C_2)—
Offset 144h............................................................................ 876
21.9.3.16Timer 2 Comparator Value Register (T2CV_1)—Offset 148h .......... 877
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
29
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