DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
18.6
18.5.17Interrupt Line Register (INTR_LINE)—Offset 3Ch ...................................... 663
18.5.18Interrupt Pin Register (INTR_PIN)—Offset 3Dh ......................................... 663
18.5.19MIN_GNT (MIN_GNT)—Offset 3Eh .......................................................... 664
18.5.20MAX_LAT (MAX_LAT)—Offset 3Fh ........................................................... 664
18.5.21Capability ID (PM_CAP_ID)—Offset 80h................................................... 664
18.5.22Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ........................... 665
18.5.23Power Management Capabilities (PMC)—Offset 82h ................................... 665
18.5.24Power Management Control/Status Register (PMCSR)—Offset 84h .............. 666
18.5.25PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h ..... 667
18.5.26Power Management Data Register (DATA_REGISTER)—Offset 87h .............. 667
18.5.27Capability ID (MSI_CAP_ID)—Offset A0h ................................................. 667
18.5.28Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h .......................... 668
18.5.29Message Control (MESSAGE_CTRL)—Offset A2h ....................................... 668
18.5.30Message Address (MESSAGE_ADDR)—Offset A4h ..................................... 668
18.5.31Message Data (MESSAGE_DATA)—Offset A8h .......................................... 669
18.5.32Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ...................................... 669
18.5.33Pending Bits for MSI (PER_VEC_PEND)—Offset B0h .................................. 670
Memory Mapped Registers................................................................................ 670
18.6.1 UART Registers .................................................................................... 670
18.6.1.1 Receive Buffer / Transmit Holding / Divisor Latch Low
(RBR_THR_DLL)—Offset 0h ...................................................... 671
18.6.1.2 Interrupt Enable / Divisor Latch High (IER_DLH)—Offset 4h.......... 671
18.6.1.3 Interrupt Identification / FIFO Control (IIR_FCR)—Offset 8h ......... 672
18.6.1.4 Line Control (LCR)—Offset Ch ................................................... 674
18.6.1.5 MODEM Control (MCR)—Offset 10h ........................................... 674
18.6.1.6 Line Status (LSR)—Offset 14h .................................................. 675
18.6.1.7 MODEM Status (MSR)—Offset 18h............................................. 677
18.6.1.8 Scratchpad (SCR)—Offset 1Ch .................................................. 678
18.6.1.9 UART Status (USR)—Offset 7Ch ................................................ 679
18.6.1.10Halt Transmission (HTX)—Offset A4h......................................... 679
18.6.1.11DMA Software Acknowledge (DMASA)—Offset A8h ...................... 680
18.6.2 DMA Controller Registers....................................................................... 680
18.6.2.1 Channel 0 Source Address (SAR0)—Offset 0h ............................. 682
18.6.2.2 Channel 0 Destination Address (DAR0)—Offset 8h ....................... 682
18.6.2.3 Channel 0 Linked List Pointer (LLP0)—Offset 10h ........................ 683
18.6.2.4 Channel 0 Control LOWER (CTL0_L)—Offset 18h ......................... 683
18.6.2.5 Channel 0 Control UPPER (CTL0_U)—Offset 1Ch.......................... 685
18.6.2.6 Channel 0 Source Status (SSTAT0)—Offset 20h .......................... 686
18.6.2.7 Channel 0 Destination Status (DSTAT0)—Offset 28h .................... 686
18.6.2.8 Channel 0 Source Status Address (SSTATAR0)—Offset 30h .......... 687
18.6.2.9 Channel 0 Destination Status Address (DSTATAR0)—Offset 38h .... 687
18.6.2.10Channel 0 Configuration LOWER (CFG0_L)—Offset 40h ................ 688
18.6.2.11Channel 0 configuration UPPER (CFG0_U)—Offset 44h ................. 689
18.6.2.12Channel 0 Source Gather (SGR0)—Offset 48h............................. 690
18.6.2.13Channel 0 Destination Scatter (DSR0)—Offset 50h ...................... 691
18.6.2.14Channel 1 Source Address (SAR1)—Offset 58h ........................... 691
18.6.2.15Channel 1 Destination Address (DAR1)—Offset 60h ..................... 692
18.6.2.16Channel 1 Linked List Pointer (LLP1)—Offset 68h ........................ 692
18.6.2.17Channel 1 Control LOWER (CTL1_L)—Offset 70h ......................... 693
18.6.2.18Channel 1 Control UPPER (CTL1_U)—Offset 74h.......................... 695
18.6.2.19Channel 1 Source Status (SSTAT1)—Offset 78h .......................... 696
18.6.2.20Channel 1 Destination Status (DSTAT1)—Offset 80h .................... 696
18.6.2.21Channel 1 Source Status Address (SSTATAR1)—Offset 88h .......... 697
18.6.2.22Channel 1 Destination Status Address (DSTATAR1)—Offset 90h .... 697
18.6.2.23Channel 1 Configuration LOWER (CFG1_L)—Offset 98h ................ 698
18.6.2.24Channel 1 configuration UPPER (CFG1_U)—Offset 9Ch ................. 699
18.6.2.25Channel 1 Source Gather (SGR1)—Offset A0h............................. 700
18.6.2.26Channel 1 Destination Scatter (DSR1)—Offset A8h ...................... 700
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
23
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