DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—
21.9.4 References........................................................................................... 877
21.10 Real Time Clock (RTC)...................................................................................... 877
21.10.1Signal Descriptions ............................................................................... 877
21.10.2Features .............................................................................................. 878
21.10.2.1Update Cycles......................................................................... 878
21.10.2.2Interrupts .............................................................................. 878
21.10.2.3Lockable RAM Ranges .............................................................. 878
21.10.3Register Map........................................................................................ 879
21.10.4I/O Registers ....................................................................................... 879
21.10.5Indexed Registers ................................................................................. 880
21.10.5.1Offset 0Ah: Register A ............................................................. 881
21.10.5.2Offset 0Bh: Register B - General Configuration ............................ 881
21.10.5.3Offset 0Ch: Register C - Flag Register ........................................ 882
21.10.5.4Offset 0Dh: Register D - Flag Register........................................ 883
21.10.6References........................................................................................... 883
21.11 Interrupt Decoding & Routing ............................................................................ 883
21.11.1Features .............................................................................................. 883
21.11.1.1Interrupt Decoder ................................................................... 883
21.11.1.2Interrupt Router...................................................................... 884
21.12 8259 Programmable Interrupt Controllers (PIC) ................................................... 884
21.12.1Features .............................................................................................. 885
21.12.1.1Interrupt Handling................................................................... 885
21.12.1.2Initialization Command Words (ICWx)........................................ 887
21.12.1.3Operation Command Words (OCW)............................................ 888
21.12.1.4Modes of Operation ................................................................. 888
21.12.1.5Masking Interrupts .................................................................. 890
21.12.1.6Steering of PCI Interrupts ........................................................ 890
21.12.2Register Map........................................................................................ 890
21.12.3I/O Registers ....................................................................................... 891
21.12.3.1Master Initialization Command Word 1 (MICW1)—Offset 20h......... 893
21.12.3.2Master Initialization Command Word 2 (MICW2)—Offset 21h......... 894
21.12.3.3Master Operational Control Word 2 (MOCW2)—Offset 24h............. 894
21.12.3.4Master Initialization Command Word 3 (MICW3)—Offset 25h......... 895
21.12.3.5Master Operational Control Word 3 (MOCW3)—Offset 28h............. 895
21.12.3.6Master Initialization Command Word 4 (MICW4)—Offset 29h......... 896
21.12.3.7Master Operational Control Word 1 (MOCW1)—Offset 2Dh ............ 897
21.12.3.8Slave Initialization Command Word 1 (SICW1)—Offset A0h........... 897
21.12.3.9Slave Initialization Command Word 2 (SICW2)—Offset A1h........... 898
21.12.3.10Slave Operational Control Word 2 (SoCW2)—Offset A4h ............. 898
21.12.3.11Slave Initialization Command Word 3 (SICW3)—Offset A5h ......... 899
21.12.3.12Slave Operational Control Word 3 (SoCW3)—Offset A8h ............. 899
21.12.3.13Slave Initialization Command Word 4 (SICW4)—Offset A9h ......... 900
21.12.3.14Slave Operational Control Word 1 (SoCW1)—Offset ADh ............. 901
21.12.3.15Master Edge/Level Control (ELCR1)—Offset 4D0h ...................... 901
21.12.3.16Slave Edge/Level Control (ELCR2)—Offset 4D1h ........................ 901
21.13 I/O APIC......................................................................................................... 903
21.13.1Features .............................................................................................. 903
21.13.2Use..................................................................................................... 904
21.13.3Unsupported Modes .............................................................................. 904
21.13.4Register Map........................................................................................ 905
21.13.5Memory Mapped Registers ..................................................................... 905
21.13.5.1Index Register (IDX)—Offset FEC00000h .................................... 906
21.13.5.2Window Register (WDW)—Offset FEC00010h .............................. 906
21.13.5.3End of Interrupt Register (EOI)—Offset FEC00040h...................... 906
21.13.6Index Registers .................................................................................... 907
21.13.6.1Identification Register (ID)—Offset 0h........................................ 907
21.13.6.2Version Register (VS)—Offset 1h ............................................... 908
Intel® Quark SoC X1000
DS
30
October 2013
Document Number: 329676-001US
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