DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—

18.6.2.27Raw Status for IntTfr Interrupt (RAW_TFR)—Offset 2C0h.............. 701

18.6.2.28Raw Status for IntBlock Interrupt (RAW_BLOCK)—Offset 2C8h ...... 701

18.6.2.29Raw Status for IntSrcTran Interrupt (RAW_SRC_TRAN)—Offset

2D0h ..................................................................................... 702

18.6.2.30Raw Status for IntDstTran Interrupt (RAW_DST_TRAN)—Offset

2D8h ..................................................................................... 702

18.6.2.31Raw Status for IntErr Interrupt (RAW_ERR)—Offset 2E0h ............. 703

18.6.2.32Status for IntTfr Interrupt (STATUS_TFR)—Offset 2E8h ................ 703

18.6.2.33Status for IntBlock Interrupt (STATUS_BLOCK)—Offset 2F0h ........ 704

18.6.2.34Status for IntSrcTran Interrupt (STATUS_SRC_TRAN)—Offset 2F8h 704

18.6.2.35Status for IntDstTran Interrupt (STATUS_DST_TRAN)—Offset 300h705

18.6.2.36Status for IntErr Interrupt (STATUS_ERR)—Offset 308h ............... 705

18.6.2.37Mask for IntTfr Interrupt (MASK_TFR)—Offset 310h ..................... 706

18.6.2.38Mask for IntBlock Interrupt (MASK_BLOCK)—Offset 318h ............. 706

18.6.2.39Mask for IntSrcTran Interrupt (MASK_SRC_TRAN)—Offset 320h .... 707

18.6.2.40Mask for IntDstTran Interrupt (MASK_DST_TRAN)—Offset 328h .... 708

18.6.2.41Mask for IntErr Interrupt (MASK_ERR)—Offset 330h .................... 708

18.6.2.42Clear for IntTfr Interrupt (CLEAR_TFR)—Offset 338h .................... 709

18.6.2.43Clear for IntBlock Interrupt (CLEAR_BLOCK)—Offset 340h ............ 709

18.6.2.44Clear for IntSrcTran Interrupt (CLEAR_SRC_TRAN)—Offset 348h ... 710

18.6.2.45Clear for IntDstTran Interrupt (CLEAR_DST_TRAN)—Offset 350h ... 710

18.6.2.46Clear for IntErr Interrupt (CLEAR_ERR)—Offset 358h ................... 711

18.6.2.47Combined Interrupt Status (STATUS_INT)—Offset 360h ............... 711

18.6.2.48Source Software Transaction Request (REQ_SRC_REG)—Offset

368h ..................................................................................... 712

18.6.2.49Destination Software Transaction Request register

(REQ_DST_REG)—Offset 370h .................................................. 712

18.6.2.50Source Single Transaction Request (SGL_REQ_SRC_REG)—Offset

378h ..................................................................................... 713

18.6.2.51Destination Single Software Transaction Request

(SGL_REQ_DST_REG)—Offset 380h ........................................... 714

18.6.2.52Source Last Transaction Request (LST_SRC_REG)—Offset 388h..... 714

18.6.2.53Destination Single Transaction Request (LST_DST_REG)—Offset

390h ..................................................................................... 715

18.6.2.54DMA Configuration (DMA_CFG_REG)—Offset 398h ....................... 715

18.6.2.55Channel Enable (CH_EN_REG)—Offset 3A0h ............................... 716

19.0 I2C* Controller/GPIO Controller ............................................................................ 717

19.1 I2C Controller.................................................................................................. 717

19.1.1 Signal Descriptions ............................................................................... 717

19.1.2 Features .............................................................................................. 717

19.1.2.1 I2C* Protocol .......................................................................... 717

19.1.2.2 I2C* Modes of Operation .......................................................... 718

19.1.2.3 Functional Description.............................................................. 718

19.1.3 Use..................................................................................................... 723

19.1.3.1 Master Mode Operation ............................................................ 723

19.1.3.2 Disabling I2C* Controller .......................................................... 723

19.1.4 References........................................................................................... 724

19.2 GPIO Controller ............................................................................................... 724

19.2.1 Signal Descriptions ............................................................................... 724

19.2.2 Features .............................................................................................. 724

19.3 Register Map................................................................................................... 724

19.4 PCI Configuration Registers............................................................................... 725

19.4.1 Vendor ID (VENDOR_ID)—Offset 0h ........................................................ 726

19.4.2 Device ID (DEVICE_ID)—Offset 2h .......................................................... 727

19.4.3 Command Register (COMMAND_REGISTER)—Offset 4h .............................. 727

19.4.4 Status Register (STATUS)—Offset 6h....................................................... 728

19.4.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .................. 728

19.4.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ....................................... 729

Intel® Quark SoC X1000

DS

24

October 2013

Document Number: 329676-001US

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