DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Introduction

Figure 1.

To enable secure applications, the SoC features an on-die Boot ROM that is used to

establish a hardware Root of Trust (RoT). The immutable code located within the Boot

ROM is used to initiate an iterative firmware authentication process ensuring only

trusted code is executed when taking the platform out of reset.

To facilitate low-cost platforms with sensitive Bill of Material (BOM) requirements, all

SoC clocks can be generated from a single crystal oscillator while all the required SoC

voltage levels can be derived from a single commercial off-the-shelf (COTS) voltage

regulator. In addition, the SoC provides an ECC-protected DRAM solution using only

standard x8 DDR3 devices.

The SoC also features a 512 Kbyte on-die embedded SRAM (eSRAM) that can be

configured to overlay regions of DRAM to provide low latency access to critical portions

of system memory. For robustness, the contents of this on-die eSRAM are also ECC

protected.

Block Diagram

CPU Core

JTAG

Host Bridge

Clock

eSRAM

DDR3

Memory

Controller

AMBA Fabric

Legacy Bridge

1.2.1

SoC CPU Core Features

• 400 MHz maximum operating frequency

• Low power options to run at half or at quarter of maximum CPU frequency

Intel® Quark SoC X1000

DS

38

October 2013

Document Number: 329676-001US

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