DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Introduction—Intel® Quark SoC X1000

1.2.2

1.2.3

1.2.4

1.2.5

1.2.6

• 32-bit address bus, 32-bit data bus

• 16 Kbyte shared instruction and data L1 cache.

System Memory Controller Features

• Single channel DDR3 memory controller with ECC support

• 16-bit data bus

• Supports up to two ranks total

• Supports DDR3 with 800 MT/s data rates

• x8 DRAM device data width

• 1 Gbit, 2 Gbit, and 4 Gbit DRAM device densities

• Total memory size from 128 Mbyte to 2 Gbyte

• Supports different physical mappings of bank addresses to optimize performance

• Out-of-order request processing to increase performance

• Aggressive power management to reduce power consumption

• Proactive page closing policies to close unused pages

• Supports soldered down DRAM devices

Embedded SRAM Features

• Low Latency 512 Kbyte on-die embedded SRAM

• Configurable to either overlay a 512 Kbyte block or overlay individual 4 Kbyte

pages of system memory

• ECC protected

Power Management Features

• Supports ACPI 3.0 specification

• Supports C0, C1, and C2 processor power states

• Supports S0, S3, and S4/S5 system power states

Security Features

• On-die Boot ROM provides Hardware Root of Trust (RoT) for firmware

authentication

PCI Express* Features

The SoC has two PCI Express* root ports, each supporting the PCI Express Base

specification Rev 2.0 at a maximum of 2.5 GT/s data transfer rates. Each root port is

configured as a x1 link.

• 128 Byte max payload size with the capability of splitting the request at 64 Byte

granularity

• Software-Initiated Link Power Management (D1, D2, D3Hot, and L1 States)

• PME event generation

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

39

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